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OMRLinkage.cpp
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OMRLinkage.cpp
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/*******************************************************************************
* Copyright (c) 2000, 2021 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#pragma csect(CODE,"TRLINKAGEBase#C")
#pragma csect(STATIC,"TRLINKAGEBase#S")
#pragma csect(TEST,"TRLINKAGEBase#T")
// See also S390Linkage2.cpp which contains more S390 Linkage
// implementations (primarily System Linkage and derived classes).
#include "codegen/Linkage.hpp"
#include <stddef.h>
#include <stdint.h>
#include "codegen/CodeGenerator.hpp"
#include "codegen/ConstantDataSnippet.hpp"
#include "env/FrontEnd.hpp"
#include "codegen/InstOpCode.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/Linkage.hpp"
#include "codegen/Linkage_inlines.hpp"
#include "codegen/LinkageConventionsEnum.hpp"
#include "codegen/LiveRegister.hpp"
#include "codegen/Machine.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/RecognizedMethods.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterConstants.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/RegisterDependencyStruct.hpp"
#include "codegen/RegisterPair.hpp"
#include "codegen/SystemLinkage.hpp"
#include "codegen/TreeEvaluator.hpp"
#include "codegen/S390Evaluator.hpp"
#include "compile/Compilation.hpp"
#include "compile/SymbolReferenceTable.hpp"
#include "control/Options.hpp"
#include "control/Options_inlines.hpp"
#include "env/CompilerEnv.hpp"
#include "env/ObjectModel.hpp"
#include "env/TRMemory.hpp"
#include "env/jittypes.h"
#include "il/AutomaticSymbol.hpp"
#include "il/Block.hpp"
#include "il/DataTypes.hpp"
#include "il/ILOpCodes.hpp"
#include "il/ILOps.hpp"
#include "il/LabelSymbol.hpp"
#include "il/MethodSymbol.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/ParameterSymbol.hpp"
#include "il/RegisterMappedSymbol.hpp"
#include "il/ResolvedMethodSymbol.hpp"
#include "il/StaticSymbol.hpp"
#include "il/Symbol.hpp"
#include "il/SymbolReference.hpp"
#include "il/TreeTop.hpp"
#include "il/TreeTop_inlines.hpp"
#include "infra/Assert.hpp"
#include "infra/BitVector.hpp"
#include "infra/List.hpp"
#include "ras/Debug.hpp"
#include "runtime/Runtime.hpp"
#include "z/codegen/CallSnippet.hpp"
#include "z/codegen/S390GenerateInstructions.hpp"
#include "z/codegen/S390HelperCallSnippet.hpp"
#include "z/codegen/S390Instruction.hpp"
#include "z/codegen/SystemLinkagezOS.hpp"
#ifdef J9_PROJECT_SPECIFIC
#include "env/VMJ9.h"
#endif
extern TR::Instruction* generateS390ImmToRegister(TR::CodeGenerator * cg, TR::Node * node, TR::Register * targetRegister,
intptr_t value, TR::Instruction * cursor);
extern bool storeHelperImmediateInstruction(TR::Node * valueChild, TR::CodeGenerator * cg, bool isReversed, TR::InstOpCode::Mnemonic op, TR::Node * node, TR::MemoryReference * mf);
////////////////////////////////////////////////////////////////////////////////
// TR::S390Linkage member functions
////////////////////////////////////////////////////////////////////////////////
OMR::Z::Linkage::Linkage(TR::CodeGenerator * codeGen)
: OMR::Linkage(codeGen),
_linkageType(TR_None), _stackSizeCheckNeeded(true), _raContextSaveNeeded(true),
_integerReturnRegister(TR::RealRegister::NoReg),
_floatReturnRegister(TR::RealRegister::NoReg),
_doubleReturnRegister(TR::RealRegister::NoReg),
_longLowReturnRegister(TR::RealRegister::NoReg),
_longHighReturnRegister(TR::RealRegister::NoReg),
_longReturnRegister(TR::RealRegister::NoReg),
_stackPointerRegister(TR::RealRegister::NoReg),
_entryPointRegister(TR::RealRegister::NoReg),
_litPoolRegister(TR::RealRegister::NoReg),
_staticBaseRegister(TR::RealRegister::NoReg),
_privateStaticBaseRegister(TR::RealRegister::NoReg),
_returnAddrRegister(TR::RealRegister::NoReg),
_raContextRestoreNeeded(true),
_firstSaved(TR::RealRegister::NoReg),
_lastSaved(TR::RealRegister::NoReg),
_lastPrologueInstr(NULL),
_firstPrologueInstr(NULL)
{
int32_t i;
self()->setProperties(0);
for (i=0; i<TR::RealRegister::NumRegisters;i++)
{
self()->setRegisterFlags(REGNUM(i),0);
}
}
/**
* Get or create the TR::Linkage object that corresponds to the given linkage
* convention.
* Even though this method is common, its implementation is machine-specific.
*/
OMR::Z::Linkage::Linkage(TR::CodeGenerator * codeGen,TR_LinkageConventions lc)
: OMR::Linkage(codeGen),
_linkageType(lc), _stackSizeCheckNeeded(true), _raContextSaveNeeded(true),
_integerReturnRegister(TR::RealRegister::NoReg),
_floatReturnRegister(TR::RealRegister::NoReg),
_doubleReturnRegister(TR::RealRegister::NoReg),
_longLowReturnRegister(TR::RealRegister::NoReg),
_longHighReturnRegister(TR::RealRegister::NoReg),
_longReturnRegister(TR::RealRegister::NoReg),
_stackPointerRegister(TR::RealRegister::NoReg),
_entryPointRegister(TR::RealRegister::NoReg),
_litPoolRegister(TR::RealRegister::NoReg),
_staticBaseRegister(TR::RealRegister::NoReg),
_privateStaticBaseRegister(TR::RealRegister::NoReg),
_returnAddrRegister(TR::RealRegister::NoReg),
_raContextRestoreNeeded(true),
_firstSaved(TR::RealRegister::NoReg),
_lastSaved(TR::RealRegister::NoReg),
_lastPrologueInstr(NULL),
_firstPrologueInstr(NULL)
{
int32_t i;
self()->setProperties(0);
for (i=0; i<TR::RealRegister::NumRegisters;i++)
{
self()->setRegisterFlags(REGNUM(i),0);
}
}
TR::Instruction *
OMR::Z::Linkage::loadUpArguments(TR::Instruction * cursor)
{
return NULL;
}
void
OMR::Z::Linkage::removeOSCOnSavedArgument(TR::Instruction* instr, TR::Register* sReg, int32_t stackOffset)
{
bool done=false;
int32_t windowSize=0;
const int32_t maxWindowSize=10;
// Start looking at the top of instruction stream body
//
TR::Instruction * current = instr->getNext();
static char *disable = feGetEnv("TR_EnableRemoveOSC");
if (!disable)
return;
if (self()->comp()->getOption(TR_TraceCG))
traceMsg(self()->comp(), "%p SP OFFSET %d, SREG %p\n",instr, stackOffset, sReg);
while ( (current != NULL) &&
!current->isLabel() &&
!current->isCall() &&
!current->isBranchOp() &&
windowSize < maxWindowSize && !done )
{
if (self()->comp()->getOption(TR_TraceCG))
traceMsg(self()->comp(), "%p inspecting\n", current);
if (current->isLoad())
{
TR::Register *tReg = ((TR::S390RXInstruction*)current)->getRegisterOperand(1);
TR::MemoryReference *mr = current->getMemoryReference();
TR::SymbolReference *symRef = mr->getSymbolReference();
TR::Symbol *sym = symRef->getSymbol();
int32_t disp = -1;
// Make sure the sym is a param
//
if (sym && sym->isRegisterMappedSymbol() && sym->getKind()==TR::Symbol::IsParameter)
{
disp = sym->castToRegisterMappedSymbol()->getOffset() + mr->getOffset();
}
TR::Instruction *newInst = NULL;
if (self()->comp()->getOption(TR_TraceCG))
traceMsg(self()->comp(), "%p is load, mrOffset %i\n",current, disp);
// Find a memRef that matches the store
//
if (disp == stackOffset)
{
TR::Instruction* prev = current->getPrev();
TR::InstOpCode::Mnemonic opCode = current->getOpCodeValue();
bool mustReplace = true;
if (opCode == TR::InstOpCode::L)
{
newInst = generateRRInstruction(self()->cg(), TR::InstOpCode::LR, current->getNode(), tReg, sReg, prev);
if (self()->comp()->getOption(TR_TraceCG))
{
traceMsg(self()->comp(), "\nProlog peeking changing TR::InstOpCode::L %s,%d(SP) to TR::InstOpCode::LR %s,%s : [%p] => [%p]\n",
tReg->getRegisterName(self()->comp()), stackOffset,
tReg->getRegisterName(self()->comp()), sReg->getRegisterName(self()->comp()), current, newInst);
}
mustReplace = false; // If sReg = treg, just delete the redundent load
}
else if (opCode == TR::InstOpCode::LG)
{
newInst = generateRRInstruction(self()->cg(), TR::InstOpCode::LGR, current->getNode(), tReg, sReg, prev);
if (self()->comp()->getOption(TR_TraceCG))
{
traceMsg(self()->comp(), "\nProlog peeking changing TR::InstOpCode::LG %s,%d(SP) to TR::InstOpCode::LGR %s,%s : [%p] => [%p]\n",
tReg->getRegisterName(self()->comp()), stackOffset,
tReg->getRegisterName(self()->comp()), sReg->getRegisterName(self()->comp()), current, newInst);
}
mustReplace = false; // If sReg = treg, just delete the redundent load
}
else if (opCode == TR::InstOpCode::LE)
{
newInst = generateRRInstruction(self()->cg(), TR::InstOpCode::LER, current->getNode(), tReg, sReg, prev);
if (self()->comp()->getOption(TR_TraceCG))
{
traceMsg(self()->comp(), "\nProlog peeking changing TR::InstOpCode::LE %s,%d(SP) to TR::InstOpCode::LER %s,%s : [%p] => [%p]\n",
tReg->getRegisterName(self()->comp()), stackOffset,
tReg->getRegisterName(self()->comp()), sReg->getRegisterName(self()->comp()), current, newInst);
}
mustReplace = false; // If sReg = treg, just delete the redundent load
}
else if (opCode == TR::InstOpCode::LD)
{
newInst = generateRRInstruction(self()->cg(), TR::InstOpCode::LDR, current->getNode(), tReg, sReg, prev);
if (self()->comp()->getOption(TR_TraceCG))
{
traceMsg(self()->comp(), "\nProlog peeking changing TR::InstOpCode::LD %s,%d(SP) to TR::InstOpCode::LDR %s,%s : [%p] => [%p]\n",
tReg->getRegisterName(self()->comp()), stackOffset,
tReg->getRegisterName(self()->comp()), sReg->getRegisterName(self()->comp()), current, newInst);
}
mustReplace = false; // If sReg = treg, just delete the redundent load
}
else if (opCode == TR::InstOpCode::LT)
{
newInst = generateRRInstruction(self()->cg(), TR::InstOpCode::LTR, current->getNode(), tReg, sReg, prev);
if (self()->comp()->getOption(TR_TraceCG))
{
traceMsg(self()->comp(), "\nProlog peeking changing TR::InstOpCode::LT %s,%d(SP) to TR::InstOpCode::LTR %s,%s : [%p] => [%p]\n",
tReg->getRegisterName(self()->comp()), stackOffset,
tReg->getRegisterName(self()->comp()), sReg->getRegisterName(self()->comp()), current, newInst);
}
}
else if (opCode == TR::InstOpCode::LTG)
{
newInst = generateRRInstruction(self()->cg(), TR::InstOpCode::LTGR, current->getNode(), tReg, sReg, prev);
if (self()->comp()->getOption(TR_TraceCG))
{
traceMsg(self()->comp(), "\nProlog peeking changing TR::InstOpCode::LTG %s,%d(SP) to TR::InstOpCode::LTGR %s,%s : [%p] => [%p]\n",
tReg->getRegisterName(self()->comp()), stackOffset,
tReg->getRegisterName(self()->comp()), sReg->getRegisterName(self()->comp()), current, newInst);
}
}
else if (opCode == TR::InstOpCode::LGF)
{
newInst = generateRRInstruction(self()->cg(), TR::InstOpCode::LGFR, current->getNode(), tReg, sReg, prev);
if (self()->comp()->getOption(TR_TraceCG))
{
traceMsg(self()->comp(), "\nProlog peeking changing TR::InstOpCode::LGF %s,%d(SP) to TR::InstOpCode::LGFR %s,%s : [%p] => [%p]\n",
tReg->getRegisterName(self()->comp()), stackOffset,
tReg->getRegisterName(self()->comp()), sReg->getRegisterName(self()->comp()), current, newInst);
}
}
// Replace if we have a new instruction
//
if (newInst &&
performTransformation(self()->comp(), "O^O : Prolog peeking removing [%p]\n", current) )
{
self()->cg()->replaceInst(current, newInst);
current = newInst;
if(!mustReplace && tReg == sReg)
{
newInst->remove();
if (self()->comp()->getOption(TR_TraceCG))
traceMsg(self()->comp(), "deleting instruction as sreg = treg\n");
}
done = true;
}
}
else if (current->matchesTargetRegister(sReg))
{
done = true;
}
}
else if (current->matchesTargetRegister(sReg))
{
done = true;
}
current=current->getNext();
windowSize++;
}
return;
}
/**
* This routine is called to save the arguments on stack when we generate
* the prolog code.
*/
void *
OMR::Z::Linkage::saveArguments(void * cursor, bool genBinary, bool InPreProlog, int32_t frameOffset, List<TR::ParameterSymbol> *parameterList
)
{
TR::RealRegister * stackPtr = self()->getNormalStackPointerRealRegister();
const bool enableVectorLinkage = self()->cg()->getSupportsVectorRegisters();
// for XPLink or FASTLINK, there are cases where the "normal" stack pointer is
// not appropriate for where to save arguments in registers.
bool useAlternateStackPointer = false;
if (self()->isXPLinkLinkageType())
{
useAlternateStackPointer = true;
}
if (useAlternateStackPointer)
{
stackPtr = self()->getStackPointerRealRegister();
}
TR::ResolvedMethodSymbol * bodySymbol = self()->comp()->getJittedMethodSymbol();
ListIterator<TR::ParameterSymbol> paramIterator((parameterList!=NULL) ? parameterList : &(bodySymbol->getParameterList()));
TR::ParameterSymbol * paramCursor;
TR::Node * firstNode = self()->comp()->getStartTree()->getNode();
TR_BitVector globalAllocatedRegisters;
TR_BitVector freeScratchable;
int32_t busyMoves[5][32];
int32_t busyIndex = 0, lastFreeIntArgIndex = 0, lastFreeFloatArgIndex = 0, lastFreeVectorArgIndex = 0, i1;
uint32_t binLocalRegs = 0x1<<14; // Binary pattern representing reg14 as free for local alloc
int8_t gprSize = self()->machine()->getGPRSize();
bool unconditionalSave = false;
// If we use preexistence or FSD or HCR, then we could be reverting back to the
// interpreter by creating prePrologue snippets. In such cases, we need
// to pass any register arguments back onto the stack, even if they are
// read-only.
// For FSD, we need to store all parameters back onto the stack.
unconditionalSave |= (InPreProlog && self()->comp()->cg()->mustGenerateSwitchToInterpreterPrePrologue());
unconditionalSave |= (self()->isForceSaveIncomingParameters() != 0);
int32_t lastReg = TR::RealRegister::LastFPR;
// Keep a list of available scratch register
// -> reset means assigned
// -> set means free
// Keep a list of global registers
//
if (enableVectorLinkage)
{
freeScratchable.init(TR::RealRegister::LastVRF + 1, self()->trMemory());
globalAllocatedRegisters.init(TR::RealRegister::LastVRF + 1, self()->trMemory());
}
else
{
freeScratchable.init(TR::RealRegister::LastFPR + 1, self()->trMemory());
globalAllocatedRegisters.init(TR::RealRegister::LastFPR + 1, self()->trMemory());
}
for (i1 = TR::RealRegister::FirstGPR; i1 <= lastReg; i1++)
{
// TODO: remove hard-coded GPR6, valid on zOS for non-XPLINK?
bool gpr6Test = (i1 >= TR::RealRegister::GPR6);
if ((gpr6Test || !self()->getPreserved(REGNUM(i1))) &&
!self()->getIntegerArgument(REGNUM(i1)) &&
!self()->getFloatArgument(REGNUM(i1)))
{
freeScratchable.set(i1);
}
}
for (paramCursor = paramIterator.getFirst(); paramCursor != NULL; paramCursor = paramIterator.getNext())
{
int32_t ai = paramCursor->getAssignedGlobalRegisterIndex();
int32_t ai_l = paramCursor->getAssignedLowGlobalRegisterIndex(); // low reg of a pair
// Contruct list of globally allocated registers
//
if (ai > 0)
{
globalAllocatedRegisters.set(ai);
}
if (ai_l > 0)
{
globalAllocatedRegisters.set(ai_l);
}
}
if (self()->isSkipGPRsForFloatParms())
{ // set GPRs skipped for FPRs to free
int32_t numIntArgs = -1, r;
for (paramCursor = paramIterator.getFirst(); paramCursor != NULL; paramCursor = paramIterator.getNext())
{
TR::DataType type = paramCursor->getType();
if (type.isFloatingPoint())
{
int32_t count = 0;
if (type.getDataType() == TR::Double
)
count = (self()->cg()->comp()->target().is64Bit()) ? 1 : 2;
else
count = 1;
for (int32_t i = 0; i < count; i++)
{
numIntArgs++;
if (numIntArgs < self()->getNumIntegerArgumentRegisters())
{
r = self()->getIntegerArgumentRegister(numIntArgs);
freeScratchable.set(r); // GPR is free (due to hole)
}
}
}
else
{
numIntArgs += (type.isInt64() && self()->cg()->comp()->target().is32Bit()) ? 2 : 1;
}
}
}
int32_t parmNum = 0;
for (paramCursor = paramIterator.getFirst(); paramCursor != NULL; paramCursor = paramIterator.getNext())
{
parmNum++;
int32_t lri = paramCursor->getLinkageRegisterIndex(); // linkage register
int32_t ai = paramCursor->getAssignedGlobalRegisterIndex(); // global reg number
TR::DataType dtype = paramCursor->getDataType();
int32_t offset = paramCursor->getParameterOffset() - frameOffset;
TR::SymbolReference * paramSymRef = NULL;
int32_t namelen = 0;
const char * param_name = NULL;
param_name = paramCursor->getTypeSignature(namelen);
// Treat GPR6 special on zLinux. It is a linkage register but also preserved.
// If it has no global reg number, locate it on local save area instead of register save area
if (self()->cg()->comp()->target().isLinux() &&
(lri > 0 && ai < 0 && (self()->getPreserved(REGNUM(lri + 3)) || dtype.isVector())))
paramCursor->setParmHasToBeOnStack();
if (self()->comp()->getOption(TR_TraceCG))
{
traceMsg(self()->comp(), "save argument: %s, lri: %d, ai: %d, offset: %d, isReferenced: %d, hasToBeOnStack: %d\n", param_name, lri, ai, offset, paramCursor->isReferencedParameter(),self()->hasToBeOnStack(paramCursor));
}
TR::InstOpCode::Mnemonic storeOpCode, loadOpCode;
uint32_t opcodeMask = 0;
bool secondStore = false;
int32_t slotSize = paramCursor->getSize();
if (self()->isSmallIntParmsAlignedRight())
{
// On both Linux and z/OS system linkages we spill both the clean and dirty bits of the incoming arguments to
// the stack if needed. The `initParamOffset` API will ensure the parameters within the method are initialized
// with offsets which point only to the clean data (no dirty bits loaded).
slotSize = gprSize;
}
if (slotSize < 4)
slotSize = 4;
switch (slotSize)
{
case 1:
storeOpCode = TR::InstOpCode::STC;
loadOpCode = TR::InstOpCode::IC;
break;
case 2:
storeOpCode = TR::InstOpCode::STH;
loadOpCode = TR::InstOpCode::ICM; // mask 3
opcodeMask = 0x3;
break;
case 3:
storeOpCode = TR::InstOpCode::STCM; // mask 7
loadOpCode = TR::InstOpCode::ICM; // mask 7
opcodeMask = 0x7;
break;
case 4:
storeOpCode = TR::InstOpCode::ST;
loadOpCode = TR::InstOpCode::L;
break;
case 8:
if (self()->cg()->comp()->target().is64Bit())
{
storeOpCode = TR::InstOpCode::STG;
loadOpCode = TR::InstOpCode::LG;
}
else
{
storeOpCode = TR::InstOpCode::ST;
secondStore = true;
loadOpCode = TR::InstOpCode::L;
}
break;
case 16:
storeOpCode = TR::InstOpCode::VST;
loadOpCode = TR::InstOpCode::VL;
break;
}
if (((self()->isSmallIntParmsAlignedRight() && paramCursor->getType().isIntegral()) ||
(self()->isPadFloatParms() && paramCursor->getType().isFloatingPoint())) && (gprSize > paramCursor->getSize()))
{
offset = offset & ~(gprSize-1);
}
// Reset "stack" pointer - which could change below
// with special register usage
stackPtr = self()->getNormalStackPointerRealRegister();
if (useAlternateStackPointer) stackPtr = self()->getStackPointerRealRegister();
// +ve lri means a linkage register is being used
//
if (lri >= 0)
{
TR::DataType type = paramCursor->getType();
TR::RealRegister::RegNum regNum;
// Long argument is completely in regs
//
bool fullLong = (type.isInt64() && lri < self()->getNumIntegerArgumentRegisters() - 1);
if (type.isFloatingPoint()) // float/double/long double
{
regNum = self()->getFloatArgumentRegister(lri);
lastFreeFloatArgIndex = lri + 1;
}
else if(self()->cg()->comp()->target().isLinux() && dtype == TR::Aggregate)
{
TR_ASSERT( paramCursor->getSize()<=8, "Only aggregates of size 8 bytes or less are passed in registers");
regNum = self()->getIntegerArgumentRegister(lri);
lastFreeIntArgIndex = lri + 1;
if(self()->cg()->comp()->target().is32Bit() && paramCursor->getSize() > 4)
{
fullLong = true; // On 31 bit this larger aggregate will be treated like a 64 bit long
lastFreeIntArgIndex++;
}
}
else if (enableVectorLinkage && dtype.isVector()) // vector type
{
regNum = self()->getVectorArgumentRegister(lri);
lastFreeVectorArgIndex = lri + 1;
}
else
{
regNum = self()->getIntegerArgumentRegister(lri);
lastFreeIntArgIndex = lri + 1;
if (fullLong && self()->cg()->comp()->target().is32Bit())
{
lastFreeIntArgIndex++;
}
}
if (self()->comp()->getOption(TR_TraceCG))
{
traceMsg(self()->comp(), "save argument: %s, regNum: %d, \n", param_name, regNum);
}
// XPLINK(STOREARGS)
if ( !paramCursor->isReferencedParameter() && !paramCursor->isParmHasToBeOnStack() &&
(!unconditionalSave || (unconditionalSave && dtype != TR::Address)) )
{
freeScratchable.set(regNum);
if (fullLong && self()->cg()->comp()->target().is32Bit())
{
freeScratchable.set(regNum + 1);
}
continue;
}
bool skipLong = false;
// Negative ai means the register is not a global, so store the argument
// off to the stack
//
// If a parameter is not referenced in the method (i.e. not used),
// then we do not have to store it back onto the stack if either:
// 1) We are not reverting back to interpreter.
// (For more details, see unconditionalSave comment above.)
// 2) We are reverting back to interpreter, and the parameter's
// type is not an address.
// 3) FSD, all parms have to be on stack, so that if method
// has breakpoint set, all values, including unreferenced parms
// will be updated by GC.
//
// For static zLinux, if you are a leaf routine, you cannot store anything on to the stack.
// This query here is actually not ideal. originally isReferencedParameter (which actually means isReferencedParameterAtIlGenTime) was replaced with isParmHasToBeOnStack, which would make sense.
// However, this broke some java modes (OSR,HCR). Likely, those modes should rely on 'unconditionalSave' to ensure we always store out to the stack for whenever we need all variables on the stack.
// This investigation will be a future todo .
if ((ai < 0 && paramCursor->isReferencedParameter()) || self()->hasToBeOnStack(paramCursor) || unconditionalSave)
{
bool regIsUsed = false;
switch (dtype)
{
case TR::Int8:
case TR::Int16:
case TR::Int32:
case TR::Address:
case TR::Int64:
case TR::Aggregate: // Should only happen on zLinux
{
if (genBinary)
{
cursor = (void *) TR::S390CallSnippet::storeArgumentItem(storeOpCode, (uint8_t *) cursor,
self()->getRealRegister(regNum), offset, self()->cg());
}
else
{
TR::MemoryReference* mr = generateS390MemoryReference(stackPtr, offset, self()->cg(), param_name);
if (storeOpCode == TR::InstOpCode::STCM)
cursor = generateRSInstruction(self()->cg(), TR::InstOpCode::STCM, firstNode, self()->getRealRegister(regNum),
opcodeMask, mr, (TR::Instruction *) cursor);
else
cursor = generateRXInstruction(self()->cg(), storeOpCode, firstNode, self()->getRealRegister(regNum),
mr, (TR::Instruction *) cursor);
((TR::Instruction*)cursor)->setBinLocalFreeRegs(binLocalRegs);
if (!InPreProlog && !globalAllocatedRegisters.isSet(regNum))
self()->removeOSCOnSavedArgument((TR::Instruction *)cursor, self()->getRealRegister(regNum), offset);
}
}
if (secondStore &&
fullLong &&
self()->cg()->comp()->target().is32Bit())
{
if (genBinary)
{
cursor = (void *) TR::S390CallSnippet::storeArgumentItem(TR::InstOpCode::ST, (uint8_t *) cursor, self()->getRealRegister(regNum),
offset, self()->cg());
}
else
{
TR::MemoryReference* mr = generateS390MemoryReference(stackPtr, offset + 4, self()->cg(), param_name);
cursor = generateRXInstruction(self()->cg(), TR::InstOpCode::ST, firstNode, self()->getRealRegister(REGNUM(regNum + 1)),
mr, (TR::Instruction *) cursor);
((TR::Instruction*)cursor)->setBinLocalFreeRegs(binLocalRegs);
if (!InPreProlog && !globalAllocatedRegisters.isSet(regNum))
self()->removeOSCOnSavedArgument((TR::Instruction *)cursor, self()->getRealRegister(regNum), offset);
}
// argument stored, so regnum is free to be used as a scratch reg
//
if (ai < 0)
{
freeScratchable.set(regNum + 1);
}
}
break;
case TR::Float:
if (genBinary)
{
cursor = (void *) TR::S390CallSnippet::storeArgumentItem(TR::InstOpCode::STE, (uint8_t *) cursor, self()->getRealRegister(regNum),
offset, self()->cg());
}
else
{
TR::MemoryReference* mr = generateS390MemoryReference(stackPtr, offset, self()->cg(), param_name);
cursor = generateRXInstruction(self()->cg(), TR::InstOpCode::STE, firstNode, self()->getRealRegister(regNum),
mr, (TR::Instruction *) cursor);
((TR::Instruction*)cursor)->setBinLocalFreeRegs(binLocalRegs);
if (!InPreProlog && !globalAllocatedRegisters.isSet(regNum))
self()->removeOSCOnSavedArgument((TR::Instruction *)cursor, self()->getRealRegister(regNum), offset);
}
break;
case TR::Double:
if (genBinary)
{
cursor = (void *) TR::S390CallSnippet::storeArgumentItem(TR::InstOpCode::STD, (uint8_t *) cursor, self()->getRealRegister(regNum),
offset, self()->cg());
}
else
{
TR::MemoryReference* mr = generateS390MemoryReference(stackPtr, offset, self()->cg(), param_name);
cursor = (void *) generateRXInstruction(self()->cg(), TR::InstOpCode::STD, firstNode, self()->getRealRegister(regNum),
mr, (TR::Instruction *) cursor);
((TR::Instruction*)cursor)->setBinLocalFreeRegs(binLocalRegs);
if (!InPreProlog && !globalAllocatedRegisters.isSet(regNum))
self()->removeOSCOnSavedArgument((TR::Instruction *)cursor, self()->getRealRegister(regNum), offset);
}
break;
case TR::VectorInt8:
case TR::VectorInt16:
case TR::VectorInt32:
case TR::VectorInt64:
case TR::VectorDouble:
if (genBinary)
{
cursor = (void *) TR::S390CallSnippet::storeArgumentItem(TR::InstOpCode::VST, (uint8_t *) cursor, self()->getRealRegister(regNum),
offset, self()->cg());
}
else
{
TR::MemoryReference* mr = generateS390MemoryReference(stackPtr, offset, self()->cg(), param_name);
cursor = generateRXInstruction(self()->cg(), TR::InstOpCode::VST, firstNode, self()->getRealRegister(regNum),
mr, (TR::Instruction *) cursor);
((TR::Instruction*)cursor)->setBinLocalFreeRegs(binLocalRegs);
if (!InPreProlog && !globalAllocatedRegisters.isSet(regNum))
self()->removeOSCOnSavedArgument((TR::Instruction *)cursor, self()->getRealRegister(regNum), offset);
}
break;
} //switch(dtype)
// argument stored, so regnum is free to be used as a scratch reg
//
if (ai < 0 )
{
freeScratchable.set(regNum);
}
}
// Global register is allocated to this argument, try and move arg to global
//
if (ai>=0 && !InPreProlog)
{
// Argument regNum is not the same as global reg so add in some register moves to fix up
// Or we have long reg on 31bir, so we need to build the 64bit register from the two
// arguments (reg + reg) or (reg + mem)
// also need to take care of longdouble/complex types which takes 2 or more slots
if (regNum != ai || (dtype == TR::Int64 && self()->cg()->comp()->target().is32Bit()))
{
// Global register is available as scratch reg, so make the move
//
if (freeScratchable.isSet(ai))
{
if (dtype == TR::Float
|| dtype == TR::Double
)
{
cursor = generateRRInstruction(self()->cg(), TR::InstOpCode::LDR, firstNode, self()->getRealRegister(REGNUM(ai)),
self()->getRealRegister(regNum), (TR::Instruction *) cursor);
((TR::Instruction*)cursor)->setBinLocalFreeRegs(binLocalRegs);
freeScratchable.reset(ai);
freeScratchable.set(regNum);
}
else
{
if (dtype == TR::Int64 && self()->cg()->comp()->target().is32Bit())
{
cursor = generateRSInstruction(self()->cg(), TR::InstOpCode::SLLG, firstNode, self()->getRealRegister(REGNUM(ai)),
self()->getRealRegister(regNum), 32, (TR::Instruction *) cursor);
if (regNum != ai)
{
freeScratchable.set(regNum);
}
freeScratchable.reset(ai);
// Figure out if the low word is passed in a reg or in memory
if (fullLong)
{
cursor = generateRRInstruction(self()->cg(), TR::InstOpCode::LR, firstNode, self()->getRealRegister(REGNUM(ai)),
self()->getRealRegister(REGNUM(regNum + 1)), (TR::Instruction *) cursor);
freeScratchable.set(regNum + 1);
}
else
{
cursor = generateRXInstruction(self()->cg(), TR::InstOpCode::L, firstNode, self()->getRealRegister(REGNUM(ai)),
generateS390MemoryReference(stackPtr, offset + 4, self()->cg()), (TR::Instruction *) cursor);
}
// Don't do anything for the low word later on as it was handled here
//
skipLong = true;
}
else
{
cursor = generateRRInstruction(self()->cg(), TR::InstOpCode::getLoadRegOpCode(), firstNode, self()->getRealRegister(REGNUM(ai)),
self()->getRealRegister(regNum), (TR::Instruction *) cursor);
freeScratchable.reset(ai);
freeScratchable.set(regNum);
}
((TR::Instruction*)cursor)->setBinLocalFreeRegs(binLocalRegs);
}
}
// Global register is not available, remember this for later
//
else
{
// Deal with the fact that the global register is not available
// We have to handle the high and low word. We use two entries
// in the busyMoves to represent high and low word.
//
if (dtype == TR::Int64 && self()->cg()->comp()->target().is32Bit())
{
if (fullLong)
{
busyMoves[0][busyIndex] = regNum;
busyMoves[1][busyIndex] = ai;
busyMoves[2][busyIndex] = 6;
busyIndex++;
busyMoves[0][busyIndex] = regNum+1;
busyMoves[1][busyIndex] = ai;
busyMoves[2][busyIndex] = 0;
busyIndex++;
}
else
{
busyMoves[0][busyIndex] = regNum;
busyMoves[1][busyIndex] = ai;
busyMoves[2][busyIndex] = 7;
busyIndex++;
busyMoves[0][busyIndex] = offset + 4;
busyMoves[1][busyIndex] = ai;
busyMoves[2][busyIndex] = 0;
busyIndex++;
}
}
else
{
busyMoves[0][busyIndex] = regNum;
busyMoves[1][busyIndex] = ai;
if (dtype == TR::Float
|| dtype == TR::Double
)
{
busyMoves[2][busyIndex] = 5;
}
else
{
busyMoves[2][busyIndex] = 0;
}
busyIndex++;
}
} // if ai is free scrachable or else..
} // if regNum !=ai
} // if ai >=0
int32_t ai_l = 0;
if (!skipLong)
ai_l = paramCursor->getAssignedLowGlobalRegisterIndex();
if (ai_l>=0 && !InPreProlog && !skipLong)
{
// Some linkages allow for the low half of the argument to be passed
// on the stack while the high work is passed in regs
//
// cases that needs reg pairs:
// - 64bit int in 32bit mode
// - complex: can pass real part in FP reg (or FP reg pair for complex long double) and imag part on stack
// - complex float / double
// - complex long double
if (!fullLong) // if long int lower word pass in stack ...
{
if (freeScratchable.isSet(ai_l))
{
cursor = generateRXInstruction(self()->cg(), TR::InstOpCode::getLoadOpCode(), firstNode, self()->getRealRegister(REGNUM(ai_l)),
generateS390MemoryReference(stackPtr, offset + 4, self()->cg()), (TR::Instruction *) cursor);
((TR::Instruction*)cursor)->setBinLocalFreeRegs(binLocalRegs);
freeScratchable.reset(ai_l);
}
// Global register is not available, remember this for later
//
else
{
busyMoves[0][busyIndex] = offset + 4;
busyMoves[1][busyIndex] = ai_l;
busyMoves[2][busyIndex] = 1;
busyMoves[3][busyIndex] = TR::InstOpCode::getLoadOpCode();
busyMoves[4][busyIndex] = 0;
busyIndex++;
}
}
// Argument regNum is not the same as global reg
// so add in some register moves to fix up
//
#ifdef J9_PROJECT_SPECIFIC
else if ((regNum+1) != ai_l)
{
// Global register is available as scratch reg, so make the move
//
if (freeScratchable.isSet(ai_l))
{
cursor = generateRRInstruction(self()->cg(), TR::InstOpCode::getLoadRegOpCode(), firstNode,
self()->getRealRegister(REGNUM(ai_l)),
self()->getRealRegister(REGNUM(regNum + 1)), (TR::Instruction *) cursor);
((TR::Instruction*)cursor)->setBinLocalFreeRegs(binLocalRegs);
freeScratchable.reset(ai_l);
freeScratchable.set(regNum + 1);
}
// Global register is not available, remember this for later
//
else
{
busyMoves[0][busyIndex] = regNum + 1;
busyMoves[1][busyIndex] = ai_l;
busyMoves[2][busyIndex] = 0;
busyIndex++;
}
}
#endif
} // if ai_l >=0
} // if lri >= 0
// lri<0: arg was passed in memory, but ai >= 0 means arg was assigned a global reg.
//
else if (ai>=0 && !InPreProlog)
{
int32_t ai_l = paramCursor->getAssignedLowGlobalRegisterIndex();
switch (dtype)
{
case TR::Int8:
case TR::Int16:
case TR::Int32:
case TR::Address:
case TR::Int64:
case TR::Aggregate: // Should only happen on zLinux
if (freeScratchable.isSet(ai))
{
TR::MemoryReference * mr = generateS390MemoryReference(stackPtr, offset, self()->cg());
if (loadOpCode == TR::InstOpCode::ICM)
cursor = generateRSInstruction(self()->cg(), TR::InstOpCode::ICM, firstNode, self()->getRealRegister(REGNUM(ai)), opcodeMask, mr, (TR::Instruction *) cursor);
else
cursor = generateRXInstruction(self()->cg(), loadOpCode, firstNode, self()->getRealRegister(REGNUM(ai)),
mr, (TR::Instruction *) cursor);
((TR::Instruction*)cursor)->setBinLocalFreeRegs(binLocalRegs);
freeScratchable.reset(ai);
}
else
{
busyMoves[0][busyIndex] = offset;
busyMoves[1][busyIndex] = ai;
busyMoves[2][busyIndex] = 1;
busyMoves[3][busyIndex] = loadOpCode;
busyMoves[4][busyIndex] = opcodeMask;
busyIndex++;