spi.rst

SPI Controller

This section describes the SPI configuration registers.

Related pins

• SDI <sdi> - E9,
• CSB <csb> - E8,
• SCK <sck> - F8,
• SDO <sdo> - F9.

reg_spi_config

Base address: 0x24000000

{ "reg": [

{"name": "prescaler", "bits": 8}, {"bits": 1, "name": "MLB"}, {"bits": 1, "name": "nCSB"}, {"bits": 1, "name": "nSCK"}, {"bits": 1, "name": "MOD"}, {"bits": 1, "name": "STM"}, {"bits": 1, "name": "IE"}, {"bits": 1, "name": "INT"}, {"bits": 1, "name": "HK"}, {"name": "(undefined, reads zero)", "type": 1, "bits": 16}],

"config": {"hspace": 1400}

}

Configuration bit definitions

Bit	Name	Values
15	Housekeeping	0 - SPI controller connected to external pins 1 - SPI controller connected directly to housekeeping SPI
14	SPI interrupt enable	0 - interrupt disabled 1 - interrupt enabled ( IRQ channel 9 <cpu_irq_channel_definitions> )
13	SPI system enable	0 - SPI disabled 1 - SPI enabled
12	stream	0 - apply/release CSB <csb> separately for each byte 1 - apply CSB <csb> until stream bit is cleared (manually)
11	mode	0 - read and change data on opposite SCK <sck> edges (default) 1 - read and change data on the same SCK <sck> edges
10	invert SCK <sck>	0 - normal SCK <sck> (default) 1 - inverted SCK <sck>
9	invert CSB <csb>	0 - normal CSB <csb> (low is active, default) 1 - inverted CSB <csb> (high is active)
8	MLB	0 - MSB first 1 - LSB first
7-0	prescaler	count (in controller clock cycles) of 1/2 SCK <sck> cycle (default value 2). Clock rate formula: SPI clock rate = 2 * core_clock / (prescaler + 1)

Note

All configuration bits other than the prescaler default to value zero.

reg_spi_data

Base address: 0x24000004

{ "reg": [

{"name": "SPI data", "bits": 8}, {"name": "(undefined, reads zero)", "type": 1, "bits": 24}]

}

The byte at 0x24000004 holds the SPI data (either read or write).

Reading to and writing from the SPI controller is simply a matter of setting the required values in the configuration register, and writing values to or reading from reg_spi_data. The protocol is similar to the UART.

A write operation will stall the CPU if an incomplete SPI transmission is still in progress.

Reading from the SPI will also stall the CPU if an incomplete SPI transmission is still in progress. There is no FIFO buffer for data. Therefore SPI reads and writes are relatively expensive operations that tie up the CPU, but will not lose or overwrite data.

Note

There is no FIFO associated with the SPI controller.