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Pre AVX2 #4

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danmoseley opened this issue Feb 27, 2019 · 3 comments
Open

Pre AVX2 #4

danmoseley opened this issue Feb 27, 2019 · 3 comments

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@danmoseley
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Nice work. As you know RyuJIT can test for ISA level support at codegen time. Do you plan to attempt to offer a SIMD codepath for CPU without AVX2? They are still fairly common I guess.

@tannergooding
@EgorBo
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EgorBo commented Feb 27, 2019

@danmosemsft thanks, yeah I am actually planning to try to make an alternative SSE-only path but I am not 100% sure it will be efficient (however there will be no penalties from mixing avx with sse and vzeroupper here and there 🙂) - the upstream project has only AVX2 based impl.

EgorBo added a commit that referenced this issue Feb 27, 2019
@EgorBo
initial SSE-impl and minor fixes (#4)
67fdc1a
@lemire
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lemire commented Mar 14, 2019

@EgorBo @danmosemsft

Pre-haswell processors are still common, sure. It is not unlikely that the performance could be decent.

@lemire
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lemire commented Jul 19, 2019

We now have support for pre-AVX cpus and for ARM NEON.

Upcoming version of simdjson will support runtime dispatch.

This may get resolved with the next version of simdjson. Upstream, simdjson will provide runtime dispatch.

cc @ioioioio

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@lemire @EgorBo @danmoseley