pareto_pwr_mre

Selected circuits

• Circuit: 8-bit unsigned adders
• Selection criteria: pareto optimal sub-set wrt. pwr and mre parameters

Parameters of selected circuits

Circuit name	MAE%	WCE%	EP%	MRE%	MSE	Download
add8u_0FP	0.00	0.00	0.00	0.00	0	[Verilog] [C]
add8u_5R3	0.039	0.20	25.00	0.14	0.2	[Verilog] [VerilogPDK45] [C]
add8u_5QL	0.16	0.59	43.75	0.40	1.5	[Verilog] [VerilogPDK45] [C]
add8u_5ME	0.35	1.37	71.88	0.94	6.5	[Verilog] [VerilogPDK45] [C]
add8u_5G5	0.78	2.93	90.62	2.08	27	[Verilog] [VerilogPDK45] [C]
add8u_2XT	1.64	4.30	96.88	4.57	100	[Verilog] [C]
add8u_0H4	3.40	9.96	98.44	9.24	432	[Verilog] [C]
add8u_06A	10.10	37.50	99.41	22.52	4292	[Verilog] [C]
add8u_063	15.29	47.66	99.61	37.63	9126	[Verilog] [C]

Parameters

References

• V. Mrazek, Z. Vasicek and R. Hrbacek, "Role of circuit representation in evolutionary design of energy-efficient approximate circuits" in IET Computers & Digital Techniques, vol. 12, no. 4, pp. 139-149, 7 2018. doi: 10.1049/iet-cdt.2017.0188
• V. Mrazek, R. Hrbacek, Z. Vasicek and L. Sekanina, "EvoApprox8b: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods". Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, Lausanne, 2017, pp. 258-261. doi: 10.23919/DATE.2017.7926993