pareto_pwr_ep

Selected circuits

• Circuit: 12-bit signed multiplier
• Selection criteria: pareto optimal sub-set wrt. pwr and ep parameters

Parameters of selected circuits

Circuit name	MAE%	WCE%	EP%	MRE%	MSE	Download
mul12s_2KL	0.00	0.00	0.00	0.00	0	[Verilog] [VerilogPDK45] [C]
mul12s_2KM	0.0000012	0.000006	25.00	0.00047	0.2	[Verilog] [VerilogPDK45] [C]
mul12s_2R1	0.0031	0.012	49.99	0.22	699051	[Verilog] [VerilogPDK45] [C]
mul12s_2K0	0.0031	0.012	62.49	0.22	699052	[Verilog] [VerilogPDK45] [C]
mul12s_35J	0.0051	0.024	74.98	0.41	13981.017e2	[Verilog] [VerilogPDK45] [C]
mul12s_2J2	0.021	0.085	87.48	1.45	24466.776e3	[Verilog] [VerilogPDK45] [C]
mul12s_2NM	0.19	0.77	98.41	12.72	18643.684e5	[Verilog] [VerilogPDK45] [C]

Parameters

References

• V. Mrazek, Z. Vasicek, L. Sekanina, H. Jiang and J. Han, "Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error" in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 11, pp. 2572-2576, Nov. 2018. doi: 10.1109/TVLSI.2018.2856362