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pareto_pwr_mre

Selected circuits

  • Circuit: 12-bit unsigned multiplier
  • Selection criteria: pareto optimal sub-set wrt. pwr and mre parameters

Parameters of selected circuits

Circuit name MAE% WCE% EP% MRE% MSE Download
mul12u_1BG 0.00 0.00 0.00 0.00 0 [Verilog] [VerilogPDK45] [C]
mul12u_08N 0.0000054 0.000006 87.50 0.00038 0.9 [Verilog] [VerilogPDK45] [C]
mul12u_2ED 0.000025 0.0001 68.75 0.0019 34 [Verilog] [VerilogPDK45] [C]
mul12u_2EE 0.000073 0.00029 81.25 0.005 248 [Verilog] [VerilogPDK45] [C]
mul12u_2EG 0.00048 0.0019 93.75 0.026 9158 [Verilog] [VerilogPDK45] [C]
mul12u_2ER 0.0071 0.028 96.86 0.16 31611.022e2 [Verilog] [VerilogPDK45] [C]
mul12u_2CN 0.031 0.12 99.68 0.87 32042.894e3 [Verilog] [VerilogPDK45] [C]
mul12u_2DU 0.18 0.73 99.90 3.29 12148.233e5 [Verilog] [VerilogPDK45] [C]
mul12u_35U 1.53 6.10 99.95 15.79 92062.713e6 [Verilog] [VerilogPDK45] [C]
mul12u_35V 18.74 74.95 99.95 87.98 15865.376e9 [Verilog] [C]

Parameters

Parameters figure

References

  • V. Mrazek, Z. Vasicek and R. Hrbacek, "Role of circuit representation in evolutionary design of energy-efficient approximate circuits" in IET Computers & Digital Techniques, vol. 12, no. 4, pp. 139-149, 7 2018. doi: 10.1049/iet-cdt.2017.0188
  • V. Mrazek, Z. Vasicek, L. Sekanina, H. Jiang and J. Han, "Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error" in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 11, pp. 2572-2576, Nov. 2018. doi: 10.1109/TVLSI.2018.2856362