- Circuit: 16-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and wce parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| mul16u_BMC | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [VerilogPDK45] [C] |
| mul16u_CG0 | 0.00000011 | 0.00000023 | 90.62 | 0.000015 | 33 | [Verilog] [VerilogPDK45] [C] |
| mul16u_C9H | 0.00000086 | 0.0000027 | 97.72 | 0.00013 | 2008 | [Verilog] [VerilogPDK45] [C] |
| mul16u_42C | 0.0000086 | 0.000037 | 98.99 | 0.00091 | 209723 | [Verilog] [VerilogPDK45] [C] |
| mul16u_F6B | 0.000075 | 0.00042 | 99.84 | 0.0067 | 16238.254e3 | [Verilog] [VerilogPDK45] [C] |
| mul16u_CK3 | 0.00073 | 0.0047 | 99.98 | 0.047 | 15307.282e5 | [Verilog] [VerilogPDK45] [C] |
| mul16u_8VH | 0.011 | 0.058 | 100.00 | 0.46 | 32818.049e7 | [Verilog] [C] |
| mul16u_GPE | 0.16 | 0.63 | 100.00 | 3.06 | 55158.891e9 | [Verilog] [VerilogPDK45] [C] |
| mul16u_H6G | 1.76 | 7.03 | 100.00 | 19.30 | 73909.015e11 | [Verilog] [VerilogPDK45] [C] |
| mul16u_HGY | 18.75 | 75.00 | 100.00 | 87.99 | 10407.645e14 | [Verilog] [C] |
- V. Mrazek, Z. Vasicek, L. Sekanina, H. Jiang and J. Han, "Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error" in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 11, pp. 2572-2576, Nov. 2018. doi: 10.1109/TVLSI.2018.2856362