README.md

Selected circuits

Circuit name	MAE_%	WCE_%	EP_%	MRE_%	MSE	Download
mul7u_01L	0.00	0.00	0.00	0.00	0	[Verilog] [C]
mul7u_03M	0.03	0.092	82.61	0.98	40	[Verilog] [C]
mul7u_0DE	0.051	0.19	87.35	1.44	115	[Verilog] [C]
mul7u_069	0.14	0.48	94.74	4.12	817	[Verilog] [C]
mul7u_093	0.24	0.99	95.40	5.32	2487	[Verilog] [C]
mul7u_09J	0.46	1.93	97.53	10.12	8789	[Verilog] [C]
mul7u_0B6	1.13	4.96	98.23	17.68	54027	[Verilog] [C]
mul7u_013	2.27	9.87	98.31	28.23	215095	[Verilog] [C]
mul7u_0CA	5.09	19.05	98.41	46.83	11107.118e2	[Verilog] [C]

V. Mrazek, S. S. Sarwar, L. Sekanina, Z. Vasicek and K. Roy, "Design of power-efficient approximate multipliers for approximate artificial neural networks," 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, 2016, pp. 1-7. doi: 10.1145/2966986.2967021