- Circuit: 12-bit signed adders (no overflow)
- Selection criteria: pareto optimal sub-set wrt. pwr and mre parameters
Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
---|---|---|---|---|---|---|
add12se_54K | 0.0049 | 0.024 | 25.00 | 0.088 | 0.2 | [Verilog] [C] |
add12se_58Y | 0.012 | 0.024 | 50.00 | 0.21 | 0.5 | [Verilog] [C] |
add12se_570 | 0.022 | 0.049 | 68.75 | 0.33 | 1.2 | [Verilog] [C] |
add12se_59E | 0.049 | 0.098 | 87.50 | 0.77 | 5.5 | [Verilog] [C] |
add12se_5AL | 0.073 | 0.22 | 90.62 | 1.15 | 14 | [Verilog] [C] |
add12se_5DG | 0.15 | 0.51 | 94.92 | 2.53 | 57 | [Verilog] [C] |
add12se_585 | 0.32 | 1.15 | 97.66 | 4.19 | 260 | [Verilog] [C] |
add12se_529 | 0.50 | 1.61 | 98.49 | 6.79 | 639 | [Verilog] [C] |
add12se_5CX | 0.81 | 2.10 | 99.22 | 12.63 | 1513 | [Verilog] [C] |
n/a