Name		Name	Last commit message	Last commit date
parent directory ..
README.md		README.md
add8s_6FR.c		add8s_6FR.c
add8s_6FR.v		add8s_6FR.v
add8s_6H2.c		add8s_6H2.c
add8s_6H2.v		add8s_6H2.v
add8s_6HF.c		add8s_6HF.c
add8s_6HF.v		add8s_6HF.v
add8s_6J2.c		add8s_6J2.c
add8s_6J2.v		add8s_6J2.v
add8s_6PM.c		add8s_6PM.c
add8s_6PM.v		add8s_6PM.v
add8s_6TR.c		add8s_6TR.c
add8s_6TR.v		add8s_6TR.v
add8s_6UN.c		add8s_6UN.c
add8s_6UN.v		add8s_6UN.v
add8s_701.c		add8s_701.c
add8s_701.v		add8s_701.v
add8s_83C.c		add8s_83C.c
add8s_83C.v		add8s_83C.v
add8s_83N.c		add8s_83N.c
add8s_83N.v		add8s_83N.v
fig.png		fig.png

README.md

Selected circuits

Circuit: 8-bit signed adders (with overflow)
Selection criteria: pareto optimal sub-set wrt. pwr and mae parameters

Parameters of selected circuits

Circuit name	MAE_%	WCE_%	EP_%	MRE_%	MSE	Download
add8s_83C	0.00	0.00	0.00	0.00	0	[Verilog] [C]
add8s_83N	0.16	1.56	12.50	1.29	0.5	[Verilog] [C]
add8s_6FR	0.39	1.56	37.30	1.48	0.7	[Verilog] [C]
add8s_6TR	0.86	3.91	66.85	4.21	2.4	[Verilog] [C]
add8s_6UN	1.88	5.47	87.50	11.76	8.4	[Verilog] [C]
add8s_6PM	3.75	9.38	93.75	26.40	35	[Verilog] [C]
add8s_6H2	6.88	25.00	99.27	40.60	110	[Verilog] [C]
add8s_6J2	12.27	33.59	98.52	75.00	343	[Verilog] [C]
add8s_701	25.47	72.66	99.11	161.98	1507	[Verilog] [C]
add8s_6HF	44.45	100.00	99.48	99.98	4551	[Verilog] [C]

Parameters

References

n/a