pareto_pwr_mse

Selected circuits

• Circuit: 8-bit unsigned adders
• Selection criteria: pareto optimal sub-set wrt. pwr and mse parameters

Parameters of selected circuits

Circuit name	MAE%	WCE%	EP%	MRE%	MSE	Download
add8u_0FP	0.00	0.00	0.00	0.00	0	[Verilog] [C]
add8u_5R3	0.039	0.20	25.00	0.14	0.2	[Verilog] [VerilogPDK45] [C]
add8u_4T8	0.098	0.20	50.00	0.27	0.5	[Verilog] [C]
add8u_5M7	0.23	0.78	76.56	0.68	2.5	[Verilog] [VerilogPDK45] [C]
add8u_5EZ	0.45	1.37	87.50	1.23	8.0	[Verilog] [VerilogPDK45] [C]
add8u_5NH	0.90	2.93	93.75	2.47	32	[Verilog] [VerilogPDK45] [C]
add8u_2XT	1.64	4.30	96.88	4.57	100	[Verilog] [C]
add8u_0H4	3.40	9.96	98.44	9.24	432	[Verilog] [C]
add8u_0CA	6.45	16.60	99.22	16.82	1488	[Verilog] [C]
add8u_8ES	8.28	25.59	99.24	25.01	2692	[Verilog] [C]
add8u_88L	19.67	50.39	99.77	49.16	14074	[Verilog] [C]

Parameters

References

• V. Mrazek, Z. Vasicek and R. Hrbacek, "Role of circuit representation in evolutionary design of energy-efficient approximate circuits" in IET Computers & Digital Techniques, vol. 12, no. 4, pp. 139-149, 7 2018. doi: 10.1049/iet-cdt.2017.0188
• V. Mrazek, R. Hrbacek, Z. Vasicek and L. Sekanina, "EvoApprox8b: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods". Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, Lausanne, 2017, pp. 258-261. doi: 10.23919/DATE.2017.7926993