README.md

Selected circuits

Circuit name	MAE_%	WCE_%	EP_%	MRE_%	MSE	Download
mul11u_001	0.00	0.00	0.00	0.00	0	[Verilog] [C]
mul11u_07G	0.019	0.098	99.71	0.80	10360.917e2	[Verilog] [C]
mul11u_0CV	0.034	0.20	99.84	1.15	31888.497e2	[Verilog] [C]
mul11u_0CY	0.09	0.47	99.87	3.00	22556.998e3	[Verilog] [C]
mul11u_06R	0.18	0.99	99.88	4.96	89807.495e3	[Verilog] [C]
mul11u_0F3	0.38	1.99	99.89	9.18	40139.971e4	[Verilog] [C]
mul11u_0DX	1.18	6.03	99.90	19.95	37290.89e5	[Verilog] [C]

V. Mrazek, S. S. Sarwar, L. Sekanina, Z. Vasicek and K. Roy, "Design of power-efficient approximate multipliers for approximate artificial neural networks," 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, 2016, pp. 1-7. doi: 10.1145/2966986.2967021