Name		Name	Last commit message	Last commit date
parent directory ..
README.md		README.md
fig.png		fig.png
mul8x5u_13K.c		mul8x5u_13K.c
mul8x5u_13K.v		mul8x5u_13K.v
mul8x5u_13N.c		mul8x5u_13N.c
mul8x5u_13N.v		mul8x5u_13N.v
mul8x5u_39T.c		mul8x5u_39T.c
mul8x5u_39T.v		mul8x5u_39T.v
mul8x5u_3M6.c		mul8x5u_3M6.c
mul8x5u_3M6.v		mul8x5u_3M6.v
mul8x5u_44B.c		mul8x5u_44B.c
mul8x5u_44B.v		mul8x5u_44B.v
mul8x5u_453.c		mul8x5u_453.c
mul8x5u_453.v		mul8x5u_453.v
mul8x5u_4E8.c		mul8x5u_4E8.c
mul8x5u_4E8.v		mul8x5u_4E8.v
mul8x5u_541.c		mul8x5u_541.c
mul8x5u_541.v		mul8x5u_541.v
mul8x5u_5R9.c		mul8x5u_5R9.c
mul8x5u_5R9.v		mul8x5u_5R9.v
mul8x5u_613.c		mul8x5u_613.c
mul8x5u_613.v		mul8x5u_613.v

README.md

Selected circuits

Circuit: 8x5-bit unsigned multiplier
Selection criteria: pareto optimal sub-set wrt. pwr and mse parameters

Parameters of selected circuits

Circuit name	MAE_%	WCE_%	EP_%	MRE_%	MSE	Download
mul8x5u_4E8	0.00	0.00	0.00	0.00	0	[Verilog] [C]
mul8x5u_5R9	0.0092	0.024	50.00	0.28	1.2	[Verilog] [C]
mul8x5u_3M6	0.026	0.11	71.36	0.69	8.6	[Verilog] [C]
mul8x5u_44B	0.073	0.28	83.25	1.85	61	[Verilog] [C]
mul8x5u_39T	0.20	0.70	91.80	4.40	434	[Verilog] [C]
mul8x5u_613	0.47	1.66	94.41	8.50	2287	[Verilog] [C]
mul8x5u_13K	1.05	3.91	95.95	20.33	11334	[Verilog] [C]
mul8x5u_13N	3.70	13.88	96.36	39.67	142736	[Verilog] [C]
mul8x5u_453	9.40	35.66	96.48	68.94	972416	[Verilog] [C]
mul8x5u_541	24.12	96.50	96.50	100.00	70690.462e2	[Verilog] [C]

Parameters

References

V. Mrazek, L. Sekanina and Z. Vasicek, "Libraries of Approximate Circuits: Design and Application in CNN Accelerators"