pareto_pwr_mae

Selected circuits

• Circuit: 12-bit unsigned multiplier
• Selection criteria: pareto optimal sub-set wrt. pwr and mae parameters

Parameters of selected circuits

Circuit name	MAE%	WCE%	EP%	MRE%	MSE	Download
mul12u_332	0.00	0.00	0.00	0.00	0	[Verilog] [VerilogPDK45] [C]
mul12u_2BR	0.0000075	0.00003	50.00	0.00062	3.8	[Verilog] [VerilogPDK45] [C]
mul12u_2BS	0.000025	0.0001	68.75	0.0019	34	[Verilog] [VerilogPDK45] [C]
mul12u_2BU	0.00019	0.00077	89.06	0.012	1574	[Verilog] [VerilogPDK45] [C]
mul12u_2BX	0.0011	0.0046	96.48	0.057	50190	[Verilog] [VerilogPDK45] [C]
mul12u_10C	0.0058	0.025	99.99	0.30	14611.25e2	[Verilog] [VerilogPDK45] [C]
mul12u_2DA	0.073	0.29	99.84	1.67	18304.091e4	[Verilog] [VerilogPDK45] [C]
mul12u_33C	0.38	1.51	99.86	5.01	56232.128e5	[Verilog] [VerilogPDK45] [C]
mul12u_2JV	2.72	10.89	99.95	26.78	27178.297e7	[Verilog] [VerilogPDK45] [C]
mul12u_34G	18.74	74.95	99.95	87.98	15865.376e9	[Verilog] [C]

Parameters

References

• V. Mrazek, Z. Vasicek, L. Sekanina, H. Jiang and J. Han, "Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error" in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 11, pp. 2572-2576, Nov. 2018. doi: 10.1109/TVLSI.2018.2856362
• V. Mrazek, Z. Vasicek and R. Hrbacek, "Role of circuit representation in evolutionary design of energy-efficient approximate circuits" in IET Computers & Digital Techniques, vol. 12, no. 4, pp. 139-149, 7 2018. doi: 10.1049/iet-cdt.2017.0188