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pareto_pwr_mse

Selected circuits

  • Circuit: 8x3-bit unsigned multiplier
  • Selection criteria: pareto optimal sub-set wrt. pwr and mse parameters

Parameters of selected circuits

Circuit name MAE% WCE% EP% MRE% MSE Download
mul8x3u_003 0.00 0.00 0.00 0.00 0 [Verilog] [C]
mul8x3u_03V 0.012 0.049 25.00 0.32 0.25 [Verilog] [C]
mul8x3u_05X 0.07 0.20 62.50 1.57 4.0 [Verilog] [C]
mul8x3u_0U7 0.14 0.44 74.37 2.79 14 [Verilog] [C]
mul8x3u_017 0.35 1.22 83.25 6.40 90 [Verilog] [C]
mul8x3u_0T6 0.89 3.22 85.79 13.98 580 [Verilog] [C]
mul8x3u_1US 1.90 6.88 86.23 24.47 2709 [Verilog] [C]
mul8x3u_0RZ 4.51 14.45 87.11 44.73 14111 [Verilog] [C]
mul8x3u_1BP 9.06 31.01 87.11 65.58 60012 [Verilog] [C]
mul8x3u_242 21.79 87.16 87.16 100.00 380056 [Verilog] [C]

Parameters

Parameters figure

References

  • V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020