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README.md

README.md

 
 

fig.png

fig.png

 
 

mul8s_1KV6.c

mul8s_1KV6.c

 
 

mul8s_1KV6.v

mul8s_1KV6.v

 
 

mul8s_1KV6_pdk45.v

mul8s_1KV6_pdk45.v

 
 

mul8s_1KVM.c

mul8s_1KVM.c

 
 

mul8s_1KVM.v

mul8s_1KVM.v

 
 

mul8s_1KVM_pdk45.v

mul8s_1KVM_pdk45.v

 
 

mul8s_1KXF.c

mul8s_1KXF.c

 
 

mul8s_1KXF.v

mul8s_1KXF.v

 
 

mul8s_1KXF_pdk45.v

mul8s_1KXF_pdk45.v

 
 

mul8s_1L12.c

mul8s_1L12.c

 
 

mul8s_1L12.v

mul8s_1L12.v

 
 

mul8s_1L12_pdk45.v

mul8s_1L12_pdk45.v

 
 

mul8s_1L2J.c

mul8s_1L2J.c

 
 

mul8s_1L2J.v

mul8s_1L2J.v

 
 

mul8s_1L2J_pdk45.v

mul8s_1L2J_pdk45.v

 
 

README.md

Selected circuits

  • Circuit: 8-bit signed multiplier
  • Selection criteria: pareto optimal sub-set wrt. pwr and ep parameters

Parameters of selected circuits

Circuit name MAE% WCE% EP% MRE% MSE Download
mul8s_1KV6 0.00 0.00 0.00 0.00 0 [Verilog] [VerilogPDK45] [C]
mul8s_1KVM 0.049 0.20 49.80 2.40 2731 [Verilog] [VerilogPDK45] [C]
mul8s_1L2J 0.081 0.39 74.61 4.41 5462 [Verilog] [VerilogPDK45] [C]
mul8s_1KXF 0.34 1.37 87.16 15.72 95576 [Verilog] [VerilogPDK45] [C]
mul8s_1L12 3.08 12.30 98.05 135.77 72829.102e2 [Verilog] [VerilogPDK45] [C]

Parameters

Parameters figure

References

  • V. Mrazek, Z. Vasicek, L. Sekanina, H. Jiang and J. Han, "Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error" in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 11, pp. 2572-2576, Nov. 2018. doi: 10.1109/TVLSI.2018.2856362