- Circuit: 8x2-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and mse parameters
Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
---|---|---|---|---|---|---|
mul8x2u_106 | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
mul8x2u_07K | 0.024 | 0.098 | 25.00 | 0.59 | 0.25 | [Verilog] [C] |
mul8x2u_0S7 | 0.067 | 0.29 | 37.50 | 1.45 | 1.5 | [Verilog] [C] |
mul8x2u_0FS | 0.23 | 0.88 | 64.06 | 4.34 | 12 | [Verilog] [C] |
mul8x2u_0ZF | 0.47 | 2.05 | 70.90 | 8.16 | 49 | [Verilog] [C] |
mul8x2u_01H | 0.83 | 4.39 | 71.78 | 11.82 | 168 | [Verilog] [C] |
mul8x2u_098 | 2.00 | 7.91 | 73.83 | 25.39 | 829 | [Verilog] [C] |
mul8x2u_0AJ | 4.25 | 18.46 | 74.32 | 45.58 | 3672 | [Verilog] [C] |
mul8x2u_0SN | 7.50 | 25.39 | 74.71 | 60.33 | 10903 | [Verilog] [C] |
mul8x2u_0NG | 18.68 | 74.71 | 74.71 | 100.00 | 76011 | [Verilog] [C] |
- V. Mrazek, L. Sekanina and Z. Vasicek, "Libraries of Approximate Circuits: Design and Application in CNN Accelerators"