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The 8080

References

Intro

Registers

Register Description
A A 8 bit register
B B 8 bit register
C C 8 bit register
D D 8 bit register
E E 8 bit register
H H 8 bit register
L L 8 bit register
SP Stack pointer (16bit)
PC Program counter (16bit)
B BC as 16 bit register
D DE as 16 bit register
H HL as 16 bit register
M memory pointed by (HL)

Flags

Flag Description
S Sign flag; set to bit 7 of result
Z Zero flag; set if the result was zero, reset otherwise
A Auxiliary Carry (AC) flag; set to carry out of bit 3 in result
P Parity flag; set if the number of bits in the result is even, and reset if it's odd
C Carry flag; set to carry out of bit 7 in result

Adrress Mode

Mode Description
abs absolute address
imm immediate (8 or 16bit)
imp implicit
ind_reg indirect via register
reg register or register pair

Instruction Groups

Group Description
arith Arithmetic instructions
branch Branch and program flow instructions
control I/O and machine control instructions
data Data transfer instructions
illegal Illegal/undocumented instructions
logic Logical instructions
stack Stack instructions

Instruction Set

OpCode List

OpCode Inst Param Group Mode Length Cycles States SZ-A-P-C Example Description
00 NOP control imp 1 1 4 ........ NOP No Operation
01 LXI B,d16 data imm 3 3 10 ........ LXI B,d16 B <- byte_3; C <- byte_2
02 STAX B data ind_reg 1 2 7 ........ STAX B (BC) <- A
03 INX B arith reg 1 1 5 ........ INX B BC <- BC + 1
04 INR B arith reg 1 1 5 SZ.A.P.. INR B B <- B + 1
05 DCR B arith reg 1 1 5 SZ.A.P.. DCR B B <- B - 1
06 MVI B,d8 data imm 2 2 7 ........ MVI B,d8 B <- byte_2
07 RLC logic imp 1 1 4 .......C RLC A <- A << 1; bit 0 <- prev bit 7; CY <- prev bit 7
08 NOP control imp 1 1 4 ........ as NOP
09 DAD B arith reg 1 3 10 .......C DAD B HL <- HL + BC
0A LDAX B data ind_reg 1 2 7 ........ LDAX B A <- (BC)
0B DCX B arith reg 1 1 5 ........ DCX B BC <- BC - 1
0C INR C arith reg 1 1 5 SZ.A.P.. INR C C <- C + 1
0D DCR C arith reg 1 1 5 SZ.A.P.. DCR C C <- C - 1
0E MVI C,d8 data imm 2 2 7 ........ MVI C,d8 C <- byte_2
0F RRC logic imp 1 1 4 .......C RRC A <- A >> 1; bit 7 <- prev bit 0; CY <- prev bit 0
10 NOP control imp 1 1 4 ........ as NOP
11 LXI D,d16 data imm 3 3 10 ........ LXI D,d16 D <- byte_3; E <- byte_2
12 STAX D data ind_reg 1 2 7 ........ STAX D (DE) <- A
13 INX D arith reg 1 1 5 ........ INX D DE <- DE + 1
14 INR D arith reg 1 1 5 SZ.A.P.. INR D D <- D + 1
15 DCR D arith reg 1 1 5 SZ.A.P.. DCR D D <- D - 1
16 MVI D,d8 data imm 2 2 7 ........ MVI D,d8 D <- byte_2
17 RAL logic imp 1 1 4 .......C RAL A <- A << 1; bit 0 <- prev CY; CY <- prev bit 7
18 NOP control imp 1 1 4 ........ as NOP
19 DAD D arith reg 1 3 10 .......C DAD D HL <- HL + DE
1A LDAX D data ind_reg 1 2 7 ........ LDAX D A <- (DE)
1B DCX D arith reg 1 1 5 ........ DCX D DE <- DE - 1
1C INR E arith reg 1 1 5 SZ.A.P.. INR E E <- E + 1
1D DCR E arith reg 1 1 5 SZ.A.P.. DCR E E <- E - 1
1E MVI E,d8 data imm 2 2 7 ........ MVI E,d8 E <- byte_2
1F RAR logic imp 1 1 4 .......C RAR A <- A >> 1; bit 7 <- prev bit 7; CY <- prev bit 0
20 NOP control imp 1 1 4 ........ as NOP
21 LXI H,d16 data imm 3 3 10 ........ LXI H,d16 H <- byte_3; L <- byte_2
22 SHLD a16 data abs 3 5 16 ........ SHLD a16 (adr) <- L; (adr + 1) <- H
23 INX H arith reg 1 1 5 ........ INX H HL <- HL + 1
24 INR H arith reg 1 1 5 SZ.A.P.. INR H H <- H + 1
25 DCR H arith reg 1 1 5 SZ.A.P.. DCR H H <- H - 1
26 MVI H,d8 data imm 2 2 7 ........ MVI H,d8 H <- byte_2
27 DAA logic imp 1 1 4 SZ.A.P.C DAA special
28 NOP control imp 1 1 4 ........ as NOP
29 DAD H arith reg 1 3 10 .......C DAD H HL <- HL + HL
2A LHLD a16 data abs 3 5 16 ........ LHLD a16 L <- (adr); H <- (adr + 1)
2B DCX H arith reg 1 1 5 ........ DCX H HL <- HL - 1
2C INR L arith reg 1 1 5 SZ.A.P.. INR L L <- L + 1
2D DCR L arith reg 1 1 5 SZ.A.P.. DCR L L <- L - 1
2E MVI L,d8 data imm 2 2 7 ........ MVI L,d8 L <- byte_2
2F CMA logic imp 1 1 4 ........ CMA A <- !A
30 NOP control imp 1 1 4 ........ as NOP
31 LXI SP,d16 data imm 3 3 10 ........ LXI SP,d16 SP.hi <- byte_3; SP.lo <- byte_2
32 STA a16 data abs 3 4 13 ........ STA a16 (adr) <- A
33 INX SP arith reg 1 1 5 ........ INX SP SP <- SP + 1
34 INR M arith ind_reg 1 3 10 SZ.A.P.. INR M (HL) <- (HL) + 1
35 DCR M arith ind_reg 1 3 10 SZ.A.P.. DCR M (HL) <- (HL) - 1
36 MVI M,d8 data ind_reg 2 3 10 ........ MVI M,d8 (HL) <- byte_2
37 STC logic imp 1 1 4 .......1 STC CY <- 1
38 NOP control imp 1 1 4 ........ as NOP
39 DAD SP arith reg 1 3 10 .......C DAD SP HL <- HL + SP
3A LDA a16 data abs 3 4 13 ........ LDA a16 A <- (adr)
3B DCX SP arith reg 1 1 5 ........ DCX SP SP <- SP - 1
3C INR A arith reg 1 1 5 SZ.A.P.. INR A A <- A + 1
3D DCR A arith reg 1 1 5 SZ.A.P.. DCR A A <- A - 1
3E MVI A,d8 data imm 2 2 7 ........ MVI A,d8 A <- byte_2
3F CMC logic imp 1 1 4 .......C CMC CY <- !CY
40 MOV B,B data reg 1 1 5 ........ MOV B,B B <- B
41 MOV B,C data reg 1 1 5 ........ MOV B,C B <- C
42 MOV B,D data reg 1 1 5 ........ MOV B,D B <- D
43 MOV B,E data reg 1 1 5 ........ MOV B,E B <- E
44 MOV B,H data reg 1 1 5 ........ MOV B,H B <- H
45 MOV B,L data reg 1 1 5 ........ MOV B,L B <- L
46 MOV B,M data ind_reg 1 2 7 ........ MOV B,M B <- (HL)
47 MOV B,A data reg 1 1 5 ........ MOV B,A B <- A
48 MOV C,B data reg 1 1 5 ........ MOV C,B C <- B
49 MOV C,C data reg 1 1 5 ........ MOV C,C C <- C
4A MOV C,D data reg 1 1 5 ........ MOV C,D C <- D
4B MOV C,E data reg 1 1 5 ........ MOV C,E C <- E
4C MOV C,H data reg 1 1 5 ........ MOV C,H C <- H
4D MOV C,L data reg 1 1 5 ........ MOV C,L C <- L
4E MOV C,M data ind_reg 1 2 7 ........ MOV C,M C <- (HL)
4F MOV C,A data reg 1 1 5 ........ MOV C,A C <- A
50 MOV D,B data reg 1 1 5 ........ MOV D,B D <- B
51 MOV D,C data reg 1 1 5 ........ MOV D,C D <- C
52 MOV D,D data reg 1 1 5 ........ MOV D,D D <- D
53 MOV D,E data reg 1 1 5 ........ MOV D,E D <- E
54 MOV D,H data reg 1 1 5 ........ MOV D,H D <- H
55 MOV D,L data reg 1 1 5 ........ MOV D,L D <- L
56 MOV D,M data ind_reg 1 2 7 ........ MOV D,M D <- (HL)
57 MOV D,A data reg 1 1 5 ........ MOV D,A D <- A
58 MOV E,B data reg 1 1 5 ........ MOV E,B E <- B
59 MOV E,C data reg 1 1 5 ........ MOV E,C E <- C
5A MOV E,D data reg 1 1 5 ........ MOV E,D E <- D
5B MOV E,E data reg 1 1 5 ........ MOV E,E E <- E
5C MOV E,H data reg 1 1 5 ........ MOV E,H E <- H
5D MOV E,L data reg 1 1 5 ........ MOV E,L E <- L
5E MOV E,M data ind_reg 1 2 7 ........ MOV E,M E <- (HL)
5F MOV E,A data reg 1 1 5 ........ MOV E,A E <- A
60 MOV H,B data reg 1 1 5 ........ MOV H,B H <- B
61 MOV H,C data reg 1 1 5 ........ MOV H,C H <- C
62 MOV H,D data reg 1 1 5 ........ MOV H,D H <- D
63 MOV H,E data reg 1 1 5 ........ MOV H,E H <- E
64 MOV H,H data reg 1 1 5 ........ MOV H,H H <- H
65 MOV H,L data reg 1 1 5 ........ MOV H,L H <- L
66 MOV H,M data ind_reg 1 2 7 ........ MOV H,M H <- (HL)
67 MOV H,A data reg 1 1 5 ........ MOV H,A H <- A
68 MOV L,B data reg 1 1 5 ........ MOV L,B L <- B
69 MOV L,C data reg 1 1 5 ........ MOV L,C L <- C
6A MOV L,D data reg 1 1 5 ........ MOV L,D L <- D
6B MOV L,E data reg 1 1 5 ........ MOV L,E L <- E
6C MOV L,H data reg 1 1 5 ........ MOV L,H L <- H
6D MOV L,L data reg 1 1 5 ........ MOV L,L L <- L
6E MOV L,M data ind_reg 1 2 7 ........ MOV L,M L <- (HL)
6F MOV L,A data reg 1 1 5 ........ MOV L,A L <- A
70 MOV M,B data ind_reg 1 2 7 ........ MOV M,B (HL) <- B
71 MOV M,C data ind_reg 1 2 7 ........ MOV M,C (HL) <- C
72 MOV M,D data ind_reg 1 2 7 ........ MOV M,D (HL) <- D
73 MOV M,E data ind_reg 1 2 7 ........ MOV M,E (HL) <- E
74 MOV M,H data ind_reg 1 2 7 ........ MOV M,H (HL) <- H
75 MOV M,L data ind_reg 1 2 7 ........ MOV M,L (HL) <- L
76 HLT control imp 1 1 7 ........ HLT special
77 MOV M,A data ind_reg 1 2 7 ........ MOV M,A (HL) <- A
78 MOV A,B data reg 1 1 5 ........ MOV A,B A <- B
79 MOV A,C data reg 1 1 5 ........ MOV A,C A <- C
7A MOV A,D data reg 1 1 5 ........ MOV A,D A <- D
7B MOV A,E data reg 1 1 5 ........ MOV A,E A <- E
7C MOV A,H data reg 1 1 5 ........ MOV A,H A <- H
7D MOV A,L data reg 1 1 5 ........ MOV A,L A <- L
7E MOV A,M data ind_reg 1 2 7 ........ MOV A,M A <- (HL)
7F MOV A,A data reg 1 1 5 ........ MOV A,A A <- A
80 ADD B arith reg 1 1 4 SZ.A.P.C ADD B A <- A + B
81 ADD C arith reg 1 1 4 SZ.A.P.C ADD C A <- A + C
82 ADD D arith reg 1 1 4 SZ.A.P.C ADD D A <- A + D
83 ADD E arith reg 1 1 4 SZ.A.P.C ADD E A <- A + E
84 ADD H arith reg 1 1 4 SZ.A.P.C ADD H A <- A + H
85 ADD L arith reg 1 1 4 SZ.A.P.C ADD L A <- A + L
86 ADD M arith ind_reg 1 2 7 SZ.A.P.C ADD M A <- A + (HL)
87 ADD A arith reg 1 1 4 SZ.A.P.C ADD A A <- A + A
88 ADC B arith reg 1 1 4 SZ.A.P.C ADC B A <- A + B + CY
89 ADC C arith reg 1 1 4 SZ.A.P.C ADC C A <- A + C + CY
8A ADC D arith reg 1 1 4 SZ.A.P.C ADC D A <- A + D + CY
8B ADC E arith reg 1 1 4 SZ.A.P.C ADC E A <- A + E + CY
8C ADC H arith reg 1 1 4 SZ.A.P.C ADC H A <- A + H + CY
8D ADC L arith reg 1 1 4 SZ.A.P.C ADC L A <- A + L + CY
8E ADC M arith ind_reg 1 2 7 SZ.A.P.C ADC M A <- A + (HL) + CY
8F ADC A arith reg 1 1 4 SZ.A.P.C ADC A A <- A + A + CY
90 SUB B arith reg 1 1 4 SZ.A.P.C SUB B A <- A - B
91 SUB C arith reg 1 1 4 SZ.A.P.C SUB C A <- A - C
92 SUB D arith reg 1 1 4 SZ.A.P.C SUB D A <- A - D
93 SUB E arith reg 1 1 4 SZ.A.P.C SUB E A <- A - E
94 SUB H arith reg 1 1 4 SZ.A.P.C SUB H A <- A - H
95 SUB L arith reg 1 1 4 SZ.A.P.C SUB L A <- A - L
96 SUB M arith ind_reg 1 2 7 SZ.A.P.C SUB M A <- A - (HL)
97 SUB A arith reg 1 1 4 SZ.A.P.C SUB A A <- A - A
98 SBB B arith reg 1 1 4 SZ.A.P.C SBB B A <- A - B - CY
99 SBB C arith reg 1 1 4 SZ.A.P.C SBB C A <- A - C - CY
9A SBB D arith reg 1 1 4 SZ.A.P.C SBB D A <- A - D - CY
9B SBB E arith reg 1 1 4 SZ.A.P.C SBB E A <- A - E - CY
9C SBB H arith reg 1 1 4 SZ.A.P.C SBB H A <- A - H - CY
9D SBB L arith reg 1 1 4 SZ.A.P.C SBB L A <- A - L - CY
9E SBB M arith ind_reg 1 2 7 SZ.A.P.C SBB M A <- A - (HL) - CY
9F SBB A arith reg 1 1 4 SZ.A.P.C SBB A A <- A - A - CY
A0 ANA B logic reg 1 1 4 SZ.A.P.0 ANA B A <- A & B
A1 ANA C logic reg 1 1 4 SZ.A.P.0 ANA C A <- A & C
A2 ANA D logic reg 1 1 4 SZ.A.P.0 ANA D A <- A & D
A3 ANA E logic reg 1 1 4 SZ.A.P.0 ANA E A <- A & E
A4 ANA H logic reg 1 1 4 SZ.A.P.0 ANA H A <- A & H
A5 ANA L logic reg 1 1 4 SZ.A.P.0 ANA L A <- A & L
A6 ANA M logic ind_reg 1 2 7 SZ.A.P.0 ANA M A <- A & (HL)
A7 ANA A logic reg 1 1 4 SZ.A.P.0 ANA A A <- A & A
A8 XRA B logic reg 1 1 4 SZ.0.P.0 XRA B A <- A ^ B
A9 XRA C logic reg 1 1 4 SZ.0.P.0 XRA C A <- A ^ C
AA XRA D logic reg 1 1 4 SZ.0.P.0 XRA D A <- A ^ D
AB XRA E logic reg 1 1 4 SZ.0.P.0 XRA E A <- A ^ E
AC XRA H logic reg 1 1 4 SZ.0.P.0 XRA H A <- A ^ H
AD XRA L logic reg 1 1 4 SZ.0.P.0 XRA L A <- A ^ L
AE XRA M logic ind_reg 1 2 7 SZ.0.P.0 XRA M A <- A ^ (HL)
AF XRA A logic reg 1 1 4 SZ.0.P.0 XRA A A <- A ^ A
B0 ORA B logic reg 1 1 4 SZ.0.P.0 ORA B A <- A
B1 ORA C logic reg 1 1 4 SZ.0.P.0 ORA C A <- A
B2 ORA D logic reg 1 1 4 SZ.0.P.0 ORA D A <- A
B3 ORA E logic reg 1 1 4 SZ.0.P.0 ORA E A <- A
B4 ORA H logic reg 1 1 4 SZ.0.P.0 ORA H A <- A
B5 ORA L logic reg 1 1 4 SZ.0.P.0 ORA L A <- A
B6 ORA M logic ind_reg 1 2 7 SZ.0.P.0 ORA M A <- A
B7 ORA A logic reg 1 1 4 SZ.0.P.0 ORA A A <- A
B8 CMP B logic reg 1 1 4 SZ.A.P.C CMP B A - B
B9 CMP C logic reg 1 1 4 SZ.A.P.C CMP C A - C
BA CMP D logic reg 1 1 4 SZ.A.P.C CMP D A - D
BB CMP E logic reg 1 1 4 SZ.A.P.C CMP E A - E
BC CMP H logic reg 1 1 4 SZ.A.P.C CMP H A - H
BD CMP L logic reg 1 1 4 SZ.A.P.C CMP L A - L
BE CMP M logic ind_reg 1 2 7 SZ.A.P.C CMP M A - (HL)
BF CMP A logic reg 1 1 4 SZ.A.P.C CMP A A - A
C0 RNZ branch imp 1 1/3 5/11 ........ RNZ if NZ, RET
C1 POP B stack reg 1 3 10 ........ POP B C <- (SP); B <- (SP + 1); SP <- SP + 2
C2 JNZ a16 branch abs 3 3 10 ........ JNZ a16 if NZ, PC <- adr
C3 JMP a16 branch abs 3 3 10 ........ JMP a16 PC <- adr
C4 CNZ a16 branch abs 3 3/5 11/17 ........ CNZ a16 if NZ, CALL adr
C5 PUSH B stack reg 1 3 11 ........ PUSH B (SP - 2) <- C; (SP - 1) <- B; SP <- SP - 2
C6 ADI d8 arith imm 2 2 7 SZ.A.P.C ADI d8 A <- A + byte_2
C7 RST 0 branch imp 1 3 11 ........ RST 0 CALL $0
C8 RZ branch imp 1 1/3 5/11 ........ RZ if Z, RET
C9 RET branch imp 1 3 10 ........ RET PC.lo <- (SP); PC.hi <- (SP + 1); SP <- SP + 2
CA JZ a16 branch abs 3 3 10 ........ JZ a16 if Z, PC <- adr
CB JMP a16 branch abs 3 3 10 ........ as JMP a16
CC CZ a16 branch abs 3 3/5 11/17 ........ CZ a16 if Z, CALL adr
CD CALL a16 branch abs 3 5 17 ........ CALL a16 (SP - 1) <- PC.hi; (SP - 2) <- PC.lo; SP <- SP - 2; PC <- adr
CE ACI d8 arith imm 2 2 7 SZ.A.P.C ACI d8 A <- A + byte_2 + CY
CF RST 1 branch imp 1 3 11 ........ RST 1 CALL $8
D0 RNC branch imp 1 1/3 5/11 ........ RNC if NCY, RET
D1 POP D stack reg 1 3 10 ........ POP D E <- (SP); D <- (SP + 1); SP <- SP + 2
D2 JNC a16 branch abs 3 3 10 ........ JNC a16 if NCY, PC <- adr
D3 OUT d8 control imm 2 3 10 ........ OUT d8 special
D4 CNC a16 branch abs 3 3/5 11/17 ........ CNC a16 if NCY, CALL adr
D5 PUSH D stack reg 1 3 11 ........ PUSH D (SP - 2) <- E; (SP - 1) <- D; SP <- SP - 2
D6 SUI d8 arith imm 2 2 7 SZ.A.P.C SUI d8 A <- A - byte_2
D7 RST 2 branch imp 1 3 11 ........ RST 2 CALL $10
D8 RC branch imp 1 1/3 5/11 ........ RC if CY, RET
D9 RET branch imp 1 3 10 ........ as RET
DA JC a16 branch abs 3 3 10 ........ JC a16 if CY, PC <- adr
DB IN d8 control imm 2 3 10 ........ IN d8 special
DC CC a16 branch abs 3 3/5 11/17 ........ CC a16 if CY, CALL adr
DD CALL a16 branch abs 3 5 17 ........ as CALL a16
DE SBI d8 arith imm 2 2 7 SZ.A.P.C SBI d8 A <- A - byte_2 - CY
DF RST 3 branch imp 1 3 11 ........ RST 3 CALL $18
E0 RPO branch imp 1 1/3 5/11 ........ RPO if PO, RET
E1 POP H stack reg 1 3 10 ........ POP H L <- (SP); H <- (SP + 1); SP <- SP + 2
E2 JPO a16 branch abs 3 3 10 ........ JPO a16 if PO, PC <- adr
E3 XTHL stack imp 1 5 18 ........ XTHL L <- > (SP); H <- > (SP + 1)
E4 CPO a16 branch abs 3 3/5 11/17 ........ CPO a16 if PO, CALL adr
E5 PUSH H stack reg 1 3 11 ........ PUSH H (SP - 2) <- L; (SP - 1) <- H; SP <- SP - 2
E6 ANI d8 logic imm 2 2 7 SZ.A.P.0 ANI d8 A <- A & byte_2
E7 RST 4 branch imp 1 3 11 ........ RST 4 CALL $20
E8 RPE branch imp 1 1/3 5/11 ........ RPE if PE, RET
E9 PCHL branch imp 1 1 5 ........ PCHL PC <- HL
EA JPE a16 branch abs 3 3 10 ........ JPE a16 if PE, PC <- adr
EB XCHG data reg 1 1 4 ........ XCHG H <- > D; L <- > E
EC CPE a16 branch abs 3 3/5 11/17 ........ CPE a16 if PE, CALL adr
ED CALL a16 branch abs 3 5 17 ........ as CALL a16
EE XRI d8 logic imm 2 2 7 SZ.0.P.0 XRI d8 A <- A ^ byte_2
EF RST 5 branch imp 1 3 11 ........ RST 5 CALL $28
F0 RP branch imp 1 1/3 5/11 ........ RP if P, RET
F1 POP PSW stack reg 1 3 10 SZ.A.P.C POP PSW flags <- (SP); A <- (SP + 1); SP <- SP + 2
F2 JP a16 branch abs 3 3 10 ........ JP a16 if P, PC <- adr
F3 DI control imp 1 1 4 ........ DI special
F4 CP a16 branch abs 3 3/5 11/17 ........ CP a16 if P, CALL adr
F5 PUSH PSW stack reg 1 3 11 ........ PUSH PSW (SP - 2) <- flags; (SP - 1) <- A; SP <- SP - 2
F6 ORI d8 logic imm 2 2 7 SZ.0.P.0 ORI d8 A <- A
F7 RST 6 branch imp 1 3 11 ........ RST 6 CALL $30
F8 RM branch imp 1 1/3 5/11 ........ RM if M, RET
F9 SPHL stack imp 1 1 5 ........ SPHL SP <- HL
FA JM a16 branch abs 3 3 10 ........ JM a16 if M, PC <- adr
FB EI control imp 1 1 4 ........ EI special
FC CM a16 branch abs 3 3/5 11/17 ........ CM a16 if M, CALL adr
FD CALL a16 branch abs 3 5 17 ........ as CALL a16
FE CPI d8 branch imm 2 2 7 SZ.A.P.C CPI d8 A - byte_2
FF RST 7 branch imp 1 3 11 ........ RST 7 CALL $38

Legenda

The duration of conditional calls and returns is different when the branch is taken or not. This is indicated by two numbers separated by “/”. The lower number (on the left side of “/”) is the duration of the instruction when there is no branch, and the higher number (on the right side of “/”) is the duration of the instruction when the branch is taken.

OpCode Table

HEX 0 1 2 3 4 5 6 7 8 9 A B C D E F
0 NOP LXI B,d16 STAX B INX B INR B DCR B MVI B,d8 RLC DAD B LDAX B DCX B INR C DCR C MVI C,d8 RRC
1 LXI D,d16 STAX D INX D INR D DCR D MVI D,d8 RAL DAD D LDAX D DCX D INR E DCR E MVI E,d8 RAR
2 LXI H,d16 SHLD a16 INX H INR H DCR H MVI H,d8 DAA DAD H LHLD a16 DCX H INR L DCR L MVI L,d8 CMA
3 LXI SP,d16 STA a16 INX SP INR M DCR M MVI M,d8 STC DAD SP LDA a16 DCX SP INR A DCR A MVI A,d8 CMC
4 MOV B,B MOV B,C MOV B,D MOV B,E MOV B,H MOV B,L MOV B,M MOV B,A MOV C,B MOV C,C MOV C,D MOV C,E MOV C,H MOV C,L MOV C,M MOV C,A
5 MOV D,B MOV D,C MOV D,D MOV D,E MOV D,H MOV D,L MOV D,M MOV D,A MOV E,B MOV E,C MOV E,D MOV E,E MOV E,H MOV E,L MOV E,M MOV E,A
6 MOV H,B MOV H,C MOV H,D MOV H,E MOV H,H MOV H,L MOV H,M MOV H,A MOV L,B MOV L,C MOV L,D MOV L,E MOV L,H MOV L,L MOV L,M MOV L,A
7 MOV M,B MOV M,C MOV M,D MOV M,E MOV M,H MOV M,L HLT MOV M,A MOV A,B MOV A,C MOV A,D MOV A,E MOV A,H MOV A,L MOV A,M MOV A,A
8 ADD B ADD C ADD D ADD E ADD H ADD L ADD M ADD A ADC B ADC C ADC D ADC E ADC H ADC L ADC M ADC A
9 SUB B SUB C SUB D SUB E SUB H SUB L SUB M SUB A SBB B SBB C SBB D SBB E SBB H SBB L SBB M SBB A
A ANA B ANA C ANA D ANA E ANA H ANA L ANA M ANA A XRA B XRA C XRA D XRA E XRA H XRA L XRA M XRA A
B ORA B ORA C ORA D ORA E ORA H ORA L ORA M ORA A CMP B CMP C CMP D CMP E CMP H CMP L CMP M CMP A
C RNZ POP B JNZ a16 JMP a16 CNZ a16 PUSH B ADI d8 RST 0 RZ RET JZ a16 CZ a16 CALL a16 ACI d8 RST 1
D RNC POP D JNC a16 OUT d8 CNC a16 PUSH D SUI d8 RST 2 RC JC a16 IN d8 CC a16 SBI d8 RST 3
E RPO POP H JPO a16 XTHL CPO a16 PUSH H ANI d8 RST 4 RPE PCHL JPE a16 XCHG CPE a16 XRI d8 RST 5
F RP POP PSW JP a16 DI CP a16 PUSH PSW ORI d8 RST 6 RM SPHL JM a16 EI CM a16 CPI d8 RST 7

Undocumented opcodes

HEX 0 1 2 3 4 5 6 7 8 9 A B C D E F
0 NOP
1 NOP NOP
2 NOP NOP
3 NOP NOP
4
5
6
7
8
9
A
B
C JMP a16
D RET CALL a16
E CALL a16
F CALL a16