forked from dwelch67/thumbulator
/
thumbulator.c
2711 lines (2499 loc) · 57.7 KB
/
thumbulator.c
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#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <getopt.h>
#include <ctype.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/socket.h>
#include <arpa/inet.h>
#include <fcntl.h>
#include <unistd.h>
#include <errno.h>
typedef int (*instruction_handler_func)(unsigned int addr, unsigned short instruction);
unsigned int read32(unsigned int);
unsigned int read_register(unsigned int);
int DBUGFETCH = 0;
int DBUGRAM = 0;
int DBUGRAMW = 0;
int DBUGREG = 0;
int DBUG = 0;
int DBUGUART = 0;
int DISS = 0;
#define RAM_START 0x20000000
#define PERIPH_START 0xE0000000
#define ROMADDMASK 0xFFFFFF
#define RAMADDMASK 0xFFFFFF
#define ROMSIZE (ROMADDMASK+1)
#define RAMSIZE (RAMADDMASK+1)
#define MAX_INPUT (64 * 1024)
unsigned short rom[ROMSIZE >> 1];
unsigned short ram[RAMSIZE >> 1];
instruction_handler_func instruction_handler[ROMSIZE];
instruction_handler_func instruction_handler_ram[RAMSIZE];
#define CPSR_N (1 << 31)
#define CPSR_Z (1 << 30)
#define CPSR_C (1 << 29)
#define CPSR_V (1 << 28)
#define CPSR_Q (1 << 27)
unsigned int entry = 0;
unsigned int systick_ctrl;
unsigned int systick_reload;
unsigned int systick_count;
unsigned int systick_calibrate;
unsigned int halfadd;
unsigned int cpsr;
unsigned int handler_mode;
unsigned int reg_norm[16]; //normal execution mode, do not have a thread mode
unsigned int cpuid;
char *output_file_name;
int read_fd;
int write_fd;
unsigned char input_buffer[MAX_INPUT];
size_t input_read_ptr = 0;
size_t input_write_ptr = 0;
int socket_fd = -1;
const char options[] = "c:o:d:m:v:p:e:";
const char *condition_str[] = {
"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", "lt", "gt", "le", "", ""
};
inline void set_instruction_handler(unsigned int pc, instruction_handler_func handler) {
if (pc < RAM_START) {
instruction_handler[(pc & ~0x08000000) - 2] = handler;
} else {
instruction_handler_ram[(pc & ~0x20000000) - 2] = handler;
}
}
inline instruction_handler_func get_instruction_handler(unsigned int pc) {
if (pc < RAM_START) {
unsigned int addr = (pc & ~0x08000000) - 2;
if (addr > ROMSIZE) {
fprintf(stderr, "ROM access out of bounds: %08x %08x\n", pc, addr);
exit(1);
}
return instruction_handler[(pc & ~0x08000000) - 2];
} else {
unsigned int addr = (pc & ~0x20000000) - 2;
if (addr > RAMSIZE) {
fprintf(stderr, "RAM access out of bounds: %08x %08x\n", pc, addr);
exit(2);
}
return instruction_handler_ram[(pc & ~0x20000000) - 2];
}
}
void dump_registers(void) {
int i;
fprintf(stderr, "Registers:\n");
for (i = 0; i < 16; i++) {
switch (i) {
case 13: fprintf(stderr, "sp: "); break;
case 14: fprintf(stderr, "lr: "); break;
case 15: fprintf(stderr, "pc: "); break;
default: fprintf(stderr, "r%d: %s", i, i < 10 ? " " : ""); break;
}
fprintf(stderr, "%08x\n", reg_norm[i]);
}
}
unsigned int fetch16(unsigned int addr)
{
unsigned int data;
if (DBUGFETCH) fprintf(stderr, "fetch16(0x%08x) = ", addr);
if (DBUG) fprintf(stderr, "fetch16(0x%08x) = ", addr);
switch(addr & 0xFF000000)
{
case 0x08000000:
addr &= ~(0x08000000);
case 0x00000000: //ROM
addr &= ROMADDMASK;
//if (addr < 0x50)
//{
// fprintf(stderr, "fetch16(0x%08x), abort\n", addr);
// exit(1);
//}
addr >>= 1;
data = rom[addr];
if (DBUGFETCH) fprintf(stderr, "0x%04x\n", data);
if (DBUG) fprintf(stderr, "0x%04x\n", data);
return (data);
case RAM_START: //RAM
addr &= RAMADDMASK;
addr >>= 1;
data = ram[addr];
if (DBUGFETCH) fprintf(stderr, "0x%04x\n", data);
if (DBUG) fprintf(stderr, "0x%04x\n", data);
return (data);
}
if (DBUG) fprintf(stderr, "fetch16(0x%08x), abort pc = 0x%04x\n", addr, read_register(15));
return 0;
}
unsigned int fetch32(unsigned int addr)
{
unsigned int data;
if (DBUGFETCH) fprintf(stderr, "fetch32(0x%08x) = ", addr);
if (DBUG) fprintf(stderr, "fetch32(0x%08x) = ", addr);
switch(addr & 0xFF000000)
{
case 0x08000000:
addr &= ~(0x08000000);
case 0x00000000: //ROM
if (addr < 0x50)
{
data = read32(addr);
if (DBUGFETCH) fprintf(stderr, "0x%08x\n", data);
if (DBUG) fprintf(stderr, "0x%08x\n", data);
if (addr == 0x00000000) return (data);
if (addr == 0x00000004) return (data);
if (addr == 0x0000003C) return (data);
fprintf(stderr, "fetch32(0x%08x), abort pc = 0x%04x\n", addr, read_register(15));
dump_registers();
exit(1);
}
case RAM_START: //RAM
//data = fetch16(addr+0);
//data |= ((unsigned int)fetch16(addr+2)) << 16;
data = read32(addr);
if (DBUGFETCH) fprintf(stderr, "0x%08x\n", data);
if (DBUG) fprintf(stderr, "0x%08x\n", data);
return (data);
}
if (DBUG) fprintf(stderr, "fetch32(0x%08x), abort pc 0x%04x\n", addr, read_register(15));
return 0;
}
void write16(unsigned int addr, unsigned int data)
{
if (DBUG) fprintf(stderr, "write16(0x%08x, 0x%04x)\n", addr, data);
switch(addr & 0xFF000000)
{
case 0x08000000:
addr &= ~(0x08000000);
case 0x00000000: //ROM
if (DBUGRAM) fprintf(stderr, "write16(0x%08x, 0x%04x)\n", addr, data);
addr &= ROMADDMASK;
addr >>= 1;
rom[addr] = data & 0xFFFF;
return;
case PERIPH_START: //periph
switch(addr)
{
case PERIPH_START:
if (DISS) printf("uart: [");
write(write_fd, &data, 1);
if (DISS) printf("]\n");
fflush(stdout);
break;
}
return;
case RAM_START: //RAM
if (DBUGRAM) fprintf(stderr, "write16(0x%08x, 0x%04x)\n", addr, data);
addr &= RAMADDMASK;
addr >>= 1;
ram[addr] = data & 0xFFFF;
return;
}
if (DBUG) fprintf(stderr, "write16(0x%08x, 0x%04x), abort pc 0x%04x\n", addr, data, read_register(15));
}
void write32(unsigned int addr, unsigned int data)
{
if (DBUG) fprintf(stderr, "write32(0x%08x, 0x%08x)\n", addr, data);
switch(addr & 0xFF000000)
{
case 0xF0000000: //halt
exit(0);
case PERIPH_START: //periph
switch(addr)
{
case PERIPH_START:
if (DISS) printf("uart: [");
write(write_fd, &data, 1);
if (DISS) printf("]\n");
fflush(stdout);
break;
case 0xE000E010:
{
unsigned int old;
old = systick_ctrl;
systick_ctrl = data & 0x00010007;
if (((old & 1) == 0) && (systick_ctrl & 1))
{
//timer started, load count
systick_count = systick_reload;
}
break;
}
case 0xE000E014:
{
systick_reload = data & 0x00FFFFFF;
break;
}
case 0xE000E018:
{
systick_count = data & 0x00FFFFFF;
break;
}
case 0xE000E01C:
{
systick_calibrate = data & 0x00FFFFFF;
break;
}
}
return;
case 0xD0000000: //debug
switch(addr & 0xFF)
{
case 0x00:
{
fprintf(stderr, "[0x%08x][0x%08x] 0x%08x\n", read_register(14), addr, data);
return;
}
case 0x10:
{
printf("0x%08x ", data);
return;
}
case 0x20:
{
printf("0x%08x\n", data);
return;
}
}
case 0x08000000:
addr &= ~(0x08000000);
case 0x00000000:
case RAM_START: //RAM
if (DBUGRAMW) fprintf(stderr, "write32(0x%08x, 0x%08x)\n", addr, data);
write16(addr+0, (data >> 0) & 0xFFFF);
write16(addr+2, (data >> 16) & 0xFFFF);
return;
}
if (DBUG) fprintf(stderr, "write32(0x%08x, 0x%08x), ignored pc 0x%04x\n", addr, data, read_register(15));
}
unsigned int read16(unsigned int addr)
{
unsigned int data;
if (DBUG) fprintf(stderr, "read16(0x%08x) = ", addr);
switch(addr & 0xFF000000)
{
case 0x08000000:
addr &= ~(0x08000000);
case 0x00000000: //ROM
addr &= ROMADDMASK;
addr >>= 1;
data = rom[addr];
if (DBUG) fprintf(stderr, "0x%04x\n", data);
return (data);
case PERIPH_START:
{
switch(addr)
{
case PERIPH_START + 4:
if (DBUGUART) printf("uart: [%d %d ", input_read_ptr, input_write_ptr);
if (input_read_ptr != input_write_ptr) {
data = input_buffer[input_read_ptr++];
if (input_read_ptr == MAX_INPUT) input_read_ptr = 0;
}
if (DBUGUART) printf("%c]\n", data);
if (DBUG) fprintf(stderr, "%08x\n", data);
return (data);
case PERIPH_START + 8:
if (input_read_ptr != input_write_ptr) {
data = -1;
} else {
data = 0;
}
if (DBUG) fprintf(stderr, "%08x\n", data);
return (data);
case PERIPH_START + 12:
{
read(read_fd, &data, 1);
}
if (DBUG) fprintf(stderr, "%08x\n", data);
return (data);
}
break;
}
case RAM_START: //RAM
if (DBUGRAM) fprintf(stderr, "read16(0x%08x) = ", addr);
addr &= RAMADDMASK;
addr >>= 1;
data = ram[addr];
if (DBUG) fprintf(stderr, "0x%04x\n", data);
if (DBUGRAM) fprintf(stderr, "0x%04x\n", data);
return (data);
}
if (DBUG) fprintf(stderr, "read16(0x%08x), abort pc 0x%04x\n", addr, read_register(15));
return 0;
}
unsigned int read32(unsigned int addr)
{
unsigned int data;
if (DBUG) fprintf(stderr, "read32(0x%08x) = ", addr);
switch(addr & 0xFF000000)
{
case 0x08000000:
addr &= ~(0x08000000);
case 0x00000000: //ROM
case RAM_START: //RAM
if (DBUGRAMW) fprintf(stderr, "read32(0x%08x) = ", addr);
data = read16(addr+0);
data |= ((unsigned int)read16(addr+2)) << 16;
if (DBUG) fprintf(stderr, "0x%08x\n", data);
if (DBUGRAMW) fprintf(stderr, "0x%08x\n", data);
return (data);
case PERIPH_START:
{
switch(addr)
{
case PERIPH_START + 4:
if (DBUGUART) printf("uart: [%d %d ", input_read_ptr, input_write_ptr);
if (input_read_ptr != input_write_ptr) {
data = input_buffer[input_read_ptr++];
if (input_read_ptr == MAX_INPUT) input_read_ptr = 0;
}
if (DBUGUART) printf("%c]\n", data);
if (DBUG) fprintf(stderr, "%08x\n", data);
return (data);
case PERIPH_START + 8:
if (input_read_ptr != input_write_ptr) {
data = -1;
} else {
data = 0;
}
if (DBUG) fprintf(stderr, "%08x\n", data);
return (data);
case PERIPH_START + 12:
{
read(read_fd, &data, 1);
}
if (DBUG) fprintf(stderr, "%08x\n", data);
return (data);
case 0xE000E010:
{
data = systick_ctrl;
systick_ctrl &= (~0x00010000);
if (DBUG) fprintf(stderr, "%08x\n", data);
return (data);
}
case 0xE000E014:
{
data = systick_reload;
if (DBUG) fprintf(stderr, "%08x\n", data);
return (data);
}
case 0xE000E018:
{
data = systick_count;
if (DBUG) fprintf(stderr, "%08x\n", data);
return (data);
}
case 0xE000E01C:
{
data = systick_calibrate;
if (DBUG) fprintf(stderr, "%08x\n", data);
return (data);
}
case 0xE000ED00:
{
data = cpuid;
if (DBUG) fprintf(stderr, "%08x\n", data);
return (data);
}
}
}
}
if (DBUG) fprintf(stderr, "read32(0x%08x), abort pc 0x%04x\n", addr, read_register(15));
return 0;
}
unsigned int read_register(unsigned int reg)
{
return reg != 15 ? reg_norm[reg] : reg_norm[reg] & ~(0x1);
}
void write_register(unsigned int reg, unsigned int data)
{
reg_norm[reg] = (reg < 15 ? data : data & ~(0x1));
}
void do_zflag(unsigned int x)
{
if (x == 0) cpsr |= CPSR_Z; else cpsr &= ~CPSR_Z;
}
void do_nflag(unsigned int x)
{
if (x & 0x80000000) cpsr |= CPSR_N; else cpsr &= ~CPSR_N;
}
void do_cflag(unsigned int a, unsigned int b, unsigned int c)
{
unsigned int rc;
cpsr &= ~CPSR_C;
rc = (a & 0x7FFFFFFF)+(b & 0x7FFFFFFF)+c; //carry in
rc = (rc >> 31)+(a >> 31)+(b >> 31); //carry out
if (rc & 2) cpsr |= CPSR_C;
}
void do_vflag(unsigned int a, unsigned int b, unsigned int c)
{
unsigned int rc;
unsigned int rd;
cpsr &= ~CPSR_V;
rc = (a & 0x7FFFFFFF)+(b & 0x7FFFFFFF)+c; //carry in
rc >>= 31; //carry in in lsbit
rd = (rc & 1)+((a >> 31) & 1)+((b >> 31) & 1); //carry out
rd >>= 1; //carry out in lsbit
rc = (rc^rd) & 1; //if carry in ! = carry out then signed overflow
if (rc) cpsr |= CPSR_V;
}
void do_cflag_bit(unsigned int x)
{
if (x) cpsr |= CPSR_C; else cpsr &= ~CPSR_C;
}
void do_vflag_bit(unsigned int x)
{
if (x) cpsr |= CPSR_V; else cpsr &= ~CPSR_V;
}
unsigned int ror_c(unsigned int x, unsigned int width, unsigned int shift)
{
unsigned int m = shift % width;
return (x >> m) | (x << (width - m));
}
unsigned int thumb_expand_imm_c(unsigned int imm)
{
unsigned int type;
unsigned int r = 0;
if (imm & 0b110000000000 == 0) {
type = (imm & 0b001100000000) >> 8;
imm &= 0xff;
switch (type) {
case 0: r = imm; break;
case 1: r = (imm << 16) | imm; break;
case 2: r = (imm << 24) | (imm << 8); break;
case 3: r = (imm << 24) | (imm << 16) | (imm << 8) | imm; break;
}
} else {
r = ror_c(0b10000000 | (imm & 0b1111111), 32, (imm & 0b111110000000) >> 7);
}
return r;
}
int condition_met(int condition)
{
switch (condition) {
case 0x0: //b eq z set
return (cpsr & CPSR_Z);
case 0x1: //b ne z clear
return (!(cpsr & CPSR_Z));
case 0x2: //b cs c set
return (cpsr & CPSR_C);
case 0x3: //b cc c clear
return (!(cpsr & CPSR_C));
case 0x4: //b mi n set
return (cpsr & CPSR_N);
case 0x5: //b pl n clear
return (!(cpsr & CPSR_N));
case 0x6: //b vs v set
return (cpsr & CPSR_V);
case 0x7: //b vc v clear
return (!(cpsr & CPSR_V));
case 0x8: //b hi c set z clear
return ((cpsr & CPSR_C) && (!(cpsr & CPSR_Z)));
case 0x9: //b ls c clear or z set
return ((cpsr & CPSR_Z) || (!(cpsr & CPSR_C)));
case 0xA: //b ge N == V
return ((cpsr & CPSR_N) && (cpsr & CPSR_V)) || ((!(cpsr & CPSR_N)) && (!(cpsr & CPSR_V)));
case 0xB: //b lt N ! = V
return ((!(cpsr & CPSR_N)) && (cpsr & CPSR_V)) || ((!(cpsr & CPSR_V)) && (cpsr & CPSR_N));
case 0xC: //b gt Z == 0 and N == V
return !(cpsr & CPSR_Z) &&
(((cpsr & CPSR_N) && (cpsr & CPSR_V)) || ((!(cpsr & CPSR_N)) && (!(cpsr & CPSR_V))));
case 0xD: //b le Z == 1 or N ! = V
return (cpsr & CPSR_Z) ||
((!(cpsr & CPSR_N)) && (cpsr & CPSR_V)) ||
((!(cpsr & CPSR_V)) && (cpsr & CPSR_N));
case 0xE:
return 1;
case 0xF:
return 0;
}
return 0;
}
void wait_for_input(void)
{
fd_set s_rd;
if (input_read_ptr == input_write_ptr) {
FD_ZERO(&s_rd);
FD_SET(read_fd, &s_rd);
select(read_fd + 1, &s_rd, NULL, NULL, NULL);
}
}
int handle_bkpt(unsigned int bp, unsigned int arg)
{
int r = 1;
FILE *f;
int s, e, n;
unsigned int sp;
sp = read_register(13);
switch (arg) {
case 0x18:
fprintf(stderr, "Exiting.\n");
break;
case 0x80:
s = read32(sp + 8);
e = read32(sp + 4);
fprintf(stderr, "Dumping from %08x to %08x into %s...\n",
s, e, output_file_name);
f = fopen(output_file_name, "wb");
while (s != e) {
n = read32(s);
fwrite(&n, 2, 1, f);
s += 2;
}
fclose(f);
write_register(13, read_register(13) + 8);
r = 0;
break;
case 0x81:
dump_registers();
r = 0;
break;
case 0x82:
wait_for_input();
r = 0;
break;
default:
fprintf(stderr, "bkpt 0x%02X %08x\n", bp, arg);
break;
}
write_register(13, read_register(13) + 4);
return r;
}
int ldr1_handler(unsigned int pc, unsigned short inst)
{
unsigned int sp;
unsigned int ra, rb, rc;
unsigned int rm, rd, rn, rs;
unsigned int op;
if (DISS) fprintf(stderr, "--- 0x%08x: 0x%04x ", (pc-4), inst);
rd = (inst >> 0) & 0x07;
rn = (inst >> 3) & 0x07;
rb = (inst >> 6) & 0x1F;
rb <<= 2;
if (DISS) fprintf(stderr, "ldr r%u, [r%u, #0x%x]\n", rd, rn, rb);
rb = read_register(rn)+rb;
rc = read32(rb);
write_register(rd, rc);
return 0;
}
int bx_handler(unsigned int pc, unsigned short inst)
{
unsigned int sp;
unsigned int ra, rb, rc;
unsigned int rm, rd, rn, rs;
unsigned int op;
if (DISS) fprintf(stderr, "--- 0x%08x: 0x%04x ", (pc-4), inst);
rm = (inst >> 3) & 0xF;
if (DISS) fprintf(stderr, "--- 0x%08x: bx r%u\n", (pc-4), rm);
rc = read_register(rm);
rc += 2;
// if (DISS) fprintf(stderr, "bx r%u 0x%x 0x%x\n", rm, rc, pc);
if (rc & 1)
{
rc &= ~1;
write_register(15, rc);
return (0);
}
else
{
fprintf(stderr, "cannot branch to ARM code at %08x (pc = 0x%08x, inst = 0x%04x)\n", rc, pc, inst);
dump_registers();
return (1);
}
return 0;
}
int add2_handler(unsigned int pc, unsigned short inst)
{
unsigned int sp;
unsigned int ra, rb, rc;
unsigned int rm, rd, rn, rs;
unsigned int op;
if (DISS) fprintf(stderr, "--- 0x%08x: 0x%04x ", (pc-4), inst);
//ADD(2) big immediate one register
rb = (inst >> 0) & 0xFF;
rd = (inst >> 8) & 0x7;
if (DISS) fprintf(stderr, "adds r%u, #0x%02X\n", rd, rb);
ra = read_register(rd);
rc = ra+rb;
write_register(rd, rc);
do_nflag(rc);
do_zflag(rc);
do_cflag(ra, rb, 0);
do_vflag(ra, rb, 0);
return (0);
}
int pop_handler(unsigned int pc, unsigned short inst) {
unsigned int sp;
unsigned int ra, rb, rc;
unsigned int rm, rd, rn, rs;
unsigned int op;
if (DISS) fprintf(stderr, "--- 0x%08x: 0x%04x ", (pc-4), inst);
if (DISS)
{
fprintf(stderr, "pop {");
for (ra = 0, rb = 0x01, rc = 0; rb; rb = (rb << 1) & 0xFF, ra++)
{
if (inst & rb)
{
if (rc) fprintf(stderr, ", ");
fprintf(stderr, "r%u", ra);
rc++;
}
}
if (inst & 0x100)
{
if (rc) fprintf(stderr, ", ");
fprintf(stderr, "pc");
}
fprintf(stderr, "}\n");
}
sp = read_register(13);
for (ra = 0, rb = 0x01; rb; rb = (rb << 1) & 0xFF, ra++)
{
if (inst & rb)
{
write_register(ra, read32(sp));
sp += 4;
}
}
if (inst & 0x100)
{
rc = read32(sp);
if ((rc & 1) == 0)
{
fprintf(stderr, "pop {rc} with an ARM address pc 0x%08x popped 0x%08x\n", pc, rc);
//exit(1);
rc &= ~1;
}
rc += 2;
write_register(15, rc);
sp += 4;
}
write_register(13, sp);
return (0);
}
int push_handler(unsigned int pc, unsigned short inst) {
unsigned int sp;
unsigned int ra, rb, rc;
unsigned int rm, rd, rn, rs;
unsigned int op;
if (DISS) fprintf(stderr, "--- 0x%08x: 0x%04x ", (pc-4), inst);
if (DISS)
{
fprintf(stderr, "push {");
for (ra = 0, rb = 0x01, rc = 0; rb; rb = (rb << 1) & 0xFF, ra++)
{
if (inst & rb)
{
if (rc) fprintf(stderr, ", ");
fprintf(stderr, "r%u", ra);
rc++;
}
}
if (inst & 0x100)
{
if (rc) fprintf(stderr, ", ");
fprintf(stderr, "lr");
}
fprintf(stderr, "}\n");
}
sp = read_register(13);
//fprintf(stderr, "sp 0x%08x\n", sp);
for (ra = 0, rb = 0x01, rc = 0; rb; rb = (rb << 1) & 0xFF, ra++)
{
if (inst & rb)
{
rc++;
}
}
if (inst & 0x100) rc++;
rc <<= 2;
sp -= rc;
rd = sp;
for (ra = 0, rb = 0x01; rb; rb = (rb << 1) & 0xFF, ra++)
{
if (inst & rb)
{
write32(rd, read_register(ra));
rd += 4;
}
}
if (inst & 0x100)
{
rc = read_register(14);
write32(rd, rc); //read_register(14));
if ((rc & 1) == 0)
{
fprintf(stderr, "push {lr} with an ARM address pc 0x%08x popped 0x%08x\n", pc, rc);
// exit(1);
}
}
write_register(13, sp);
return (0);
}
int default_thumb2_handler(unsigned int pc, unsigned short inst)
{
unsigned int sp;
unsigned int ra, rb, rc;
unsigned int rm, rd, rn, rs;
unsigned int op, op1, op2, inst2;
inst2 = fetch16(pc - 2);
op1 = (inst & 0x1800) >> 11;
op2 = (inst & 0x07f0) >> 4;
op = (inst2 & 0xf000) >> 15;
//fprintf(stderr, "Thumb-2: %01x %07x %01x\n", op1, op2, op);
//BL(Thumb-2)
switch (op1) {
case 2:
if (op == 1) {
int j1, j2, s, imm_hi, imm_lo, offset;
op = (inst2 & 0x3000) >> 12;
offset = 0;
s = (inst & 0x400) >> 10;
j1 = (inst2 & 0x2000) >> 13;
j2 = (inst2 & 0x800) >> 11;
if ((op & 0x5) == 0 && (op2 & 0x38) != 0x38) {
int cond = (inst & 0x3c0);
if (condition_met(cond >> 6)) {
struct {signed int x:20;} ext;
imm_hi = (inst & 0x3F);
imm_lo = (inst2 & 0x7FF);
offset = (s << 20) + (!(j1 ^ s) << 19) + (!(j2 ^ s) << 18) + (imm_hi << 12) | (imm_lo << 1);
offset = (ext.x = offset) + 1;
}
if (DISS) fprintf(stderr, "--- 0x%08x: b%s.w %08x\n", (pc - 4), condition_str[cond], pc + offset);
} else if ((op & 0x5) == 1) {
struct {signed int x:24;} ext;
imm_hi = (inst & 0x3FF);
imm_lo = (inst2 & 0x7FF);
offset = (s << 24) + (!(j1 ^ s) << 23) + (!(j2 ^ s) << 22) + (imm_hi << 12) | (imm_lo << 1);
offset = (ext.x = offset) + 1;
write_register(14, pc | 1);
if (DISS) fprintf(stderr, "--- 0x%08x: bl %08x\n", (pc - 4), pc + offset);
}
if (offset) {
if ((pc + 2 + offset) & 1) {
rc &= ~1;
write_register(15, pc + 2 + offset);
return (0);
} else {
fprintf(stderr, "cannot branch to ARM location %08x (pc = 0x%08x, inst = 0x%04x)\n",
pc + 2 + offset + 1, pc, inst);
return (1);
}
} else {
write_register(15, pc + 2);
return 0;
}
} else {
if ((op2 & 0b010000) == 0b010000) {
} else {
int op, rd, imm8, imm3, i;
op = (inst >> 4) & 0x1e;
rd = (inst2 >> 8) & 0xf;
rn = inst & 0xf;
imm3 = (inst2 >> 12) & 0x7; imm8 = (inst2 & 0xff); i = (inst >> 10) & 0x1;
//fprintf(stderr, "Thumb-2: op = %02x rd = %1x rn = %1x i = %d\n", op, rd, rn, i);
switch (op) {
case 4: if (rn != 15) {
if (!i) {
write_register(rd, read_register(rn) | (imm3 << 8) | imm8);
write_register(15, pc + 2);
return (0);
}
} else {
write_register(rd, thumb_expand_imm_c((i << 11) | (imm3 << 8) | imm8));
write_register(15, pc + 2);
return (0);
}
break;
}
}
fprintf(stderr, "Thumb-2 instruction 0x%0x %04x at 0x%08x not implemented (1)\n", inst, inst2, pc - 4);
return (1);
}
break;
case 1:
fprintf(stderr, "Thumb-2 instruction 0x%0x %04x at 0x%08x not implemented (2)\n", inst, inst2, pc - 4);
return (1);
case 3:
if ((op2 & 0x38) == 0x38) {
op1 = (inst >> 4) & 0x7;
op2 = (inst2 >> 4) & 0xf;
switch (op1) {
case 1:
if (op2 == 0xf) {
rn = inst & 0xf;
rm = inst2 & 0xf;
rd = (inst2 >> 8) & 0xf;
write_register(rd, (int) read_register(rn) / (int) read_register(rm));
write_register(15, pc + 2);
return 0;
}
break;
case 3:
rn = inst & 0xf;
rm = inst2 & 0xf;
rd = (inst2 >> 8) & 0xf;
write_register(rd, (unsigned int) read_register(rn) / (unsigned int) read_register(rm));
write_register(15, pc + 2);
return 0;
default:
fprintf(stderr, "Thumb-2: %02x %02x\n", op1, op2);
break;
}
} else if ((op2 & 0x38) == 0x30) {
int ra;
op1 = (inst >> 4) & 0x7;
op2 = (inst2 >> 4) & 0x3;
ra = (inst2 >> 12) & 0xf;
switch (op1) {
case 0:
rn = inst & 0xf;
rm = inst2 & 0xf;
rd = (inst2 >> 8) & 0xf;
ra = (inst2 >> 12) & 0xf;
if (op2 == 0) {
if (ra == 0xf) {
} else {
}
} else {
write_register(rd, read_register(ra) - read_register(rm) * read_register(rn));
write_register(15, pc + 2);
return (0);
}
default:
fprintf(stderr, "Thumb-2: %01x %07x %01x\n", op1, op2, ra);
break;
}
} else if ((op2 & 0x67) == 0x05) {
op1 = (inst >> 7) & 0x3;
op2 = (inst2 >> 6) & 0x3f;
rn = (inst & 0xf);
//fprintf(stderr, "Thumb-2: %01x %07x %01x\n", op1, op2, rn);
if (rn == 0xf) {
int rt, imm12, u;
rt = (inst2 >> 12) & 0xf;
imm12 = inst2 & 0x7ff;
u = (inst >> 6) & 0x1;
imm12 = inst2 & 0x7ff;
write_register(rt, read32(read_register(15) + (u ? imm12 : -imm12)));
write_register(15, pc + 2);
return (0);
} else {
if (op1 == 0x00 && op2 == 0x00) {
} else if (op1 == 0x00 && (((op2 & 0x24) == 0x24) || ((op2 & 0b111100) == 0b110000))) {
} else if (op1 == 0x01) {
int rt, imm12;
rt = (inst2 >> 12) & 0xf;
imm12 = inst2 & 0x7ff;
write_register(rt, read32(read_register(rn) + imm12));
write_register(15, read_register(15) + 2);
return (0);
}
}
} else if ((op2 & 0b1110001) == 0b0000000) {
op1 = (inst >> 5) & 0x7;
op2 = (inst2 >> 6) & 0x3f;
rn = inst & 0xf;
//fprintf(stderr, "Thumb-2: %01x %07x %1x\n", op1, op2, rn);
if (op1 == 0x3) {
} else if (op1 == 0x2) {
if ((op2 & 0b100000) == 0b100000) {
int rt, imm8, p, u, w;
rt = (inst2 >> 12) & 0xf;
imm8 = inst2 & 0xff;
p = (inst2 >> 10) & 0x1;
u = (inst2 >> 9) & 0x1;
w = (inst2 >> 8) & 0x1;
write32(read_register(rn) + (p ? (u ? imm8 : -imm8) : 0), read_register(rt));
if (w) write_register(rn, read_register(rn) + (u ? imm8 : -imm8));
write_register(15, pc + 2);
return (0);
} else {
}
}