add RISC-V architecture support

[frantony]

RISC-V is a new and very promising open instruction set architecture.

[kandeshvari]

Are there public MCs or CPUs available?

[frantony]

There is a RISCV32 HiFive1 board.
For RISCV64 please see HiFive Unleashed board.

You can use mainline qemu for HiFive board emulation.

[kandeshvari]

1. What arch is better to get as a base for porting? Is generic a stub for any new arch?
2. What other code I have to write besides src/arch?

[anton-bondarev]

@kandeshvari In my mind, now the easiest arch implementation is ppc.

• First of all porting is required boot code and linker script for memory mapping, After ones you can debug with 'gdb' on 'qemu'.
• Next step is usually implementing diag interface for 'printf'.
• Timers, interrupts and so on you can implement later

There is graduation thesis about porting process (in Russian)

[kandeshvari]

I'm trying to build minimal kernel as it described here

my template:

package genconfig

configuration conf {
	@Runlevel(2) include embox.arch.riscv.kernel.boot
	@Runlevel(2) include embox.arch.riscv.kernel.arch
	@Runlevel(2) include embox.arch.system(core_freq=3200000000)

	@Runlevel(2) include embox.kernel.spinlock(spin_debug=false)
	@Runlevel(2) include embox.driver.serial.sifive_uart(base_addr=0x10013000,baud_rate=115200,clock_freq=32000000)
	@Runlevel(2) include embox.driver.diag(impl="embox__driver__serial__sifive_uart")
	@Runlevel(2) include embox.driver.interrupt.no_interrupts
}

next:

make confload-riscv/qemu-sifive-e
make

but gain an error:

In file included from src/s_fma.c:31:0:
/home/dk/devel/other/embox/build/extbld/third_party/lib/OpenLibm/openlibm-2252cbd02c176a31f74fa10f8fcdf926c3124987/include/openlibm_fenv.h:16:2: error: #error "Unsupported platform"

Do I really need libm for minimal kernel? How to switch it's build off?

[alexkalmuk]

@kandeshvari Probably, you can try include embox.compat.libc.math_libm_none

[anton-bondarev]

@kandeshvari And use add line
include embox.compat.libc.stdio.print(support_floating=0)

for switch off floating point support in 'print' routines

[anton-bondarev]

@kandeshvari

Probably, you can try include embox.compat.libc.math_libm_none

try to use include embox.compat.libc.math_builtins

[nastya-nizharadze]

Hi, @kandeshvari
I'm going to continue porting Embox to RISC-V architecture. It would be great if you could tell me what results have already been achieved.

[kandeshvari]

Hi @nastya-nizharadze

Plz see in https://github.com/kandeshvari/embox/tree/risc-v-support

I've done early stage with qemu-sifive-e
I've added boot code and diag_serial via sifive's uart. It boots now and shows

Embox kernel start
runlevel: init level is 0
runlevel: init level is 1
	unit: initializing embox.driver.clock.clint_timer: CPU frequency: 16000000
done
runlevel: init level is 2
runlevel: init level is 3
runlevel: init level is 4

Next I started interrupts but switched to other private tasks and abandoned this one :(

some hints to help:

compile risc-v qemu

./configure --target-list=riscv32-softmmu,riscv64-softmmu --extra-cflags="-std=gnu99"
make -j 4

risc-v baremetal examples

https://github.com/michaeljclark/riscv-probe

disasm

# show symbols
objdump --syms label-test.o
riscv32-unknown-elf-objdump -d build/base/bin/embox | less

qemu gdb

# terminate qemu -> CTRL-A, X
qemu-system-riscv32 -nographic -machine sifive_e -kernel build/base/bin/embox -s -S
riscv32-unknown-elf-gdb -x gdb.script build/base/bin/embox

$ cat gdb.script 
target remote localhost:1234

Good luck!

[kandeshvari]

more notes:

resources

[Tuesday @ 0900 RISC V Interrupts Krste Asanović, UC Berkeley & SiFive Inc](https://www.youtube.com/watch?v=iPbaG_wnNJY)

interrupts

[FE310G: an open source RISC-V microcontroller – Interrupt System](http://embeddedsystems.io/fe310g-open-source-riscv-microcontroller-interrupt-system/)

https://www.sifive.com/blog/all-aboard-part-3-linker-relaxation-in-riscv-toolchain

[nastya-nizharadze]

Thank you very much, @kandeshvari !

[anton-bondarev]

Hi @kandeshvari!

Plz see in https://github.com/kandeshvari/embox/tree/risc-v-support

I've done early stage with qemu-sifive-e
I've added boot code and diag_serial via sifive's uart. It boots now and shows

Looks great. Thank you. May you create PR for your current achievements?

[kandeshvari]

@anton-bondarev,
sure, give me few days to prepare PR.

[kandeshvari]

@anton-bondarev,
need help ;)
embox/src/compat/libc/include/inttypes.h:192 - how these defines were constructed? I can't find e2k or mips in code

[anton-bondarev]

@kandeshvari
Do you mean
#if defined (__e2k__) || (defined(__mips__) && !defined(__gnu_linux__)) || defined(__sparc__) || defined(__microblaze__) || defined(__PPC__)
?

These macros _e2k_ or __PPC__ predefined in cross-compilers (<arch>-gcc) . We check type of architecture for defining some integer types. It's may be different for different cross-compilers for the same arch. MIPS for example:
(defined(__mips__) && !defined(__gnu_linux__))
and
(defined(__mips__) && defined(__gnu_linux__))
in line 212

In the first case we use mips-elf-gcc from own build https://github.com/embox/crosstool In the other case we use mips-linux-gcc from debian repository.

I think for risc-v you should print the predefined macros from your gcc https://stackoverflow.com/questions/2224334/gcc-dump-preprocessor-defines
And add to appropriate #if #else branch it depends of uint32_t and other types declarations

[kandeshvari]

I've removed embox.driver.clock.clint_timer from PR due to jiffies_init() has added to clock_source.c. jiffies_init() needs to use interrupt timer that I don't have at the moment. I only started to add interrupts and tried to use hz clock_source that can't be used now.

[anton-bondarev]

I've removed embox.driver.clock.clint_timer from PR

Not a problem.

Thanks a lot for your work! PR will be merged soon!

[anton-bondarev]

Now Embox has support for several RISC-V platforms. therefore the issue is closed. It will open new issues for others RISC-V features