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Hello,
I’m using XU1 Module with PE1 Baseboard. After following the User Documentation for Enclustra Build Environment, I could boot the Linux without any problem.
After that I made some change to PL using Vivado by adding AXI Ethernet Lite Mac to FPGA design, so that a new .bit file was generated.
According to the mentioned User Documentation I should now change the path to .bit file in Build Environment to let it generate a new .bin file. But I also need new device tree blob because a new node in system (Ethernet Lite MAC). Unfortunately the Build Environment doesn’t update the dtb.
Is there any option to generate new dtb using Enclustra Build Environment after introducing new changes to FPGA PL?
Thanks!
The text was updated successfully, but these errors were encountered:
Usam95
changed the title
Generating a new device tree after changing the fpga design
Generate a new device tree after changing the fpga design
Apr 3, 2019
Hello,
I’m using XU1 Module with PE1 Baseboard. After following the User Documentation for Enclustra Build Environment, I could boot the Linux without any problem.
After that I made some change to PL using Vivado by adding AXI Ethernet Lite Mac to FPGA design, so that a new .bit file was generated.
According to the mentioned User Documentation I should now change the path to .bit file in Build Environment to let it generate a new .bin file. But I also need new device tree blob because a new node in system (Ethernet Lite MAC). Unfortunately the Build Environment doesn’t update the dtb.
Is there any option to generate new dtb using Enclustra Build Environment after introducing new changes to FPGA PL?
Thanks!
The text was updated successfully, but these errors were encountered: