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hdmi_tx_hw.c
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hdmi_tx_hw.c
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/*
* Amlogic Meson HDMI Transmitter Driver
* Copyright (C) 2010 Amlogic, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the named License,
* or any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/version.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/mm.h>
#include <linux/major.h>
#include <linux/platform_device.h>
#include <linux/mutex.h>
#include <linux/cdev.h>
#include <linux/slab.h>
//#include <linux/amports/canvas.h>
#include <asm/uaccess.h>
#include <asm/delay.h>
#include <mach/am_regs.h>
#include <mach/clock.h>
#include <mach/power_gate.h>
#include <linux/clk.h>
#include <mach/clock.h>
#include <linux/amlogic/vout/vinfo.h>
#include <linux/amlogic/vout/enc_clk_config.h>
#include <linux/amlogic/vout/vout_notify.h>
#include <mach/io.h>
#include <mach/register.h>
#ifdef CONFIG_PANEL_IT6681
#include <linux/it6681.h>
#endif
#include <linux/amlogic/hdmi_tx/hdmi_info_global.h>
#include <linux/amlogic/hdmi_tx/hdmi_tx_module.h>
#include <linux/amlogic/hdmi_tx/hdmi_tx_cec.h>
#if 0 //todo
#include "../hdmi_tx_hdcp.h"
#include "../hdmi_tx_compliance.h"
#endif
#include <mach/hdmi_tx_reg.h>
#include "tvenc_conf.h"
#ifdef Wr
#undef Wr
#endif
#ifdef Rd
#undef Rd
#endif
#define Wr(reg,val) WRITE_MPEG_REG(reg,val)
#define Rd(reg) READ_MPEG_REG(reg)
#define Wr_reg_bits(reg, val, start, len) \
Wr(reg, (Rd(reg) & ~(((1L<<(len))-1)<<(start)))|((unsigned int)(val) << (start)))
#define EDID_RAM_ADDR_SIZE (4*128)
static void hdmi_audio_init(unsigned char spdif_flag);
static void hdmitx_dump_tvenc_reg(int cur_VIC, int printk_flag);
static void hdmi_phy_suspend(void);
static void hdmi_phy_wakeup(hdmitx_dev_t* hdmitx_device);
unsigned char hdmi_pll_mode = 0; /* 1, use external clk as hdmi pll source */
static unsigned char aud_para = 0x49;
#define HSYNC_POLARITY 1 // HSYNC polarity: active high
#define VSYNC_POLARITY 1 // VSYNC polarity: active high
#define TX_INPUT_COLOR_DEPTH 0 // Pixel bit width: 0=24-bit; 1=30-bit; 2=36-bit; 3=48-bit.
#define TX_INPUT_COLOR_FORMAT 1 // Pixel format: 0=RGB444; 1=YCbCr444; 2=Rsrv; 3=YCbCr422.
#define TX_INPUT_COLOR_RANGE 0 // Pixel range: 0=16-235/240; 1=16-240; 2=1-254; 3=0-255.
#define TX_OUTPUT_COLOR_RANGE 0 // Pixel range: 0=16-235/240; 1=16-240; 2=1-254; 3=0-255.
#if 1
//spdif
#define TX_I2S_SPDIF 0 // 0=SPDIF; 1=I2S.
#define TX_I2S_8_CHANNEL 0 // 0=I2S 2-channel; 1=I2S 4 x 2-channel.
#else
//i2s 8 channel
#define TX_I2S_SPDIF 1 // 0=SPDIF; 1=I2S.
#define TX_I2S_8_CHANNEL 1 // 0=I2S 2-channel; 1=I2S 4 x 2-channel.
#endif
//static struct tasklet_struct EDID_tasklet;
static unsigned delay_flag = 0;
static unsigned serial_reg_val=0x1; //0x22;
static unsigned char i2s_to_spdif_flag=1; // if current channel number is larger than 2ch, using i2s
static unsigned color_depth_f=0;
static unsigned color_space_f=0;
static unsigned char new_reset_sequence_flag=1;
static unsigned char power_mode=1;
static unsigned char power_off_vdac_flag=0;
/* 0, do not use fixed tvenc val for all mode; 1, use fixed tvenc val mode for 480i; 2, use fixed tvenc val mode for all modes */
static unsigned char use_tvenc_conf_flag=1;
static unsigned char cur_vout_index = 1; //CONFIG_AM_TV_OUTPUT2
static void hdmi_tx_mode_ctrl(HDMI_Video_Codes_t vic)
{
switch(vic) {
// Interlaced Mode
case HDMI_480i60:
case HDMI_480i60_16x9:
case HDMI_576i50:
case HDMI_576i50_16x9:
CLK_GATE_ON(CTS_ENCI);
CLK_GATE_ON(VCLK2_VENCI1);
CLK_GATE_ON(VCLK2_ENCI);
CLK_GATE_OFF(CTS_ENCP);
CLK_GATE_ON(CTS_HDMI_TX_PIXEL);
hdmi_set_reg_bits(OTHER_BASE_ADDR + HDMI_OTHER_CTRL1, 1, 15, 1);
break;
case HDMI_Unkown:
CLK_GATE_OFF(CTS_ENCP);
CLK_GATE_OFF(CTS_HDMI_TX_PIXEL);
hdmi_set_reg_bits(OTHER_BASE_ADDR + HDMI_OTHER_CTRL1, 0, 15, 1);
break;
// Progressive Mode
default:
CLK_GATE_OFF(CTS_ENCI);
CLK_GATE_ON(CTS_ENCP);
CLK_GATE_ON(CTS_HDMI_TX_PIXEL);
hdmi_set_reg_bits(OTHER_BASE_ADDR + HDMI_OTHER_CTRL1, 1, 15, 1);
break;
}
}
static void hdmi_tx_gate_pwr_ctrl(enum hd_ctrl cmd, void * data)
{
hdmi_print(IMP, SYS "gate/pwr cmd: %d\n", cmd);
switch(cmd) {
case VID_EN:
{
hdmitx_dev_t* hdmitx_device = (hdmitx_dev_t *)data;
hdmi_tx_mode_ctrl(hdmitx_device->cur_VIC);
}
break;
case VID_DIS:
hdmi_tx_mode_ctrl(HDMI_Unkown);
break;
case AUD_EN:
if(i2s_to_spdif_flag == 1) {
hdmi_set_reg_bits(OTHER_BASE_ADDR + HDMI_OTHER_CTRL1, 0, 13, 1);
}
else {
hdmi_set_reg_bits(OTHER_BASE_ADDR + HDMI_OTHER_CTRL1, 1, 13, 1);
}
aml_set_reg32_bits(P_AIU_HDMI_CLK_DATA_CTRL, 2, 0, 2);
aml_set_reg32_bits(P_HHI_MEM_PD_REG0, 0, 10, 2);
break;
case AUD_DIS:
hdmi_set_reg_bits(OTHER_BASE_ADDR + HDMI_OTHER_CTRL1, 0, 13, 1);
aml_set_reg32_bits(P_AIU_HDMI_CLK_DATA_CTRL, 0, 0, 2);
aml_set_reg32_bits(P_HHI_MEM_PD_REG0, 3, 10, 2);
break;
case EDID_EN:
aml_set_reg32_bits(P_HHI_MEM_PD_REG0, 0, 8, 2);
break;
case EDID_DIS:
aml_set_reg32_bits(P_HHI_MEM_PD_REG0, 3, 8, 2);
break;
case HDCP_EN:
aml_set_reg32_bits(P_HHI_MEM_PD_REG0, 0, 12, 2);
break;
case HDCP_DIS:
aml_set_reg32_bits(P_HHI_MEM_PD_REG0, 3, 12, 2);
break;
}
}
static unsigned long modulo(unsigned long a, unsigned long b)
{
if (a >= b) {
return(a-b);
} else {
return(a);
}
}
static signed int to_signed(unsigned int a)
{
if (a <= 7) {
return(a);
} else {
return(a-16);
}
}
static void delay_us (int us)
{
//udelay(us);
if(delay_flag&0x1)
mdelay((us+999)/1000);
else
udelay(us);
} /* delay_us */
#if 0
static irqreturn_t intr_handler(int irq, void *dev_instance)
{
unsigned int data32;
hdmitx_dev_t* hdmitx_device = (hdmitx_dev_t*)dev_instance;
data32 = hdmi_rd_reg(OTHER_BASE_ADDR + HDMI_OTHER_INTR_STAT);
hdmi_print(IMP, SYS "irq %x\n", data32);
if(hdmitx_device->hpd_lock == 1) {
hdmi_wr_reg(OTHER_BASE_ADDR + HDMI_OTHER_INTR_STAT_CLR, 0xf);
hdmi_print(IMP, HPD "HDMI hpd locked\n");
return IRQ_HANDLED;
}
if(hdmitx_device->internal_mode_change == 1){ // if the irq from the internal mode change, just do nothing and return
hdmi_wr_reg(OTHER_BASE_ADDR + HDMI_OTHER_INTR_STAT_CLR, 0x7);
hdmi_print(IMP, SYS "hdmitx: ignore irq\n");
return IRQ_HANDLED;
}
WRITE_MPEG_REG(HHI_GCLK_MPEG2, READ_MPEG_REG(HHI_GCLK_MPEG2) | (1<<4)); //Enable HDMI PCLK
if (data32 & (1 << 1)) { //HPD falling
hdmitx_device->vic_count = 0;
hdmi_wr_only_reg(OTHER_BASE_ADDR + HDMI_OTHER_INTR_STAT_CLR, 1 << 1); //clear HPD falling interrupt in hdmi module
hdmitx_device->hpd_event = 2;
}
if (data32 & (1 << 0)) { //HPD rising
hdmi_wr_only_reg(OTHER_BASE_ADDR + HDMI_OTHER_INTR_STAT_CLR, 1 << 0); //clear HPD rising interrupt in hdmi module
// If HPD asserts, then start DDC transaction
if (hdmi_rd_reg(TX_HDCP_ST_EDID_STATUS) & (1<<1)) {
// Start DDC transaction
hdmitx_device->cur_edid_block=0;
hdmitx_device->cur_phy_block_ptr=0;
hdmitx_device->hpd_event = 1;
// Error if HPD deasserts
} else {
hdmi_print(ERR, HPD "HPD deasserts!\n");
}
}
if (data32 & (1 << 2)) { //TX EDID interrupt
if((hdmitx_device->cur_edid_block+2)<=EDID_MAX_BLOCK){
int ii, jj;
for(jj=0;jj<2;jj++){
for(ii=0;ii<128;ii++){
hdmitx_device->EDID_buf[hdmitx_device->cur_edid_block*128+ii]
=hdmi_rd_reg(0x600+hdmitx_device->cur_phy_block_ptr*128+ii);
}
hdmitx_device->cur_edid_block++;
hdmitx_device->cur_phy_block_ptr++;
hdmitx_device->cur_phy_block_ptr=hdmitx_device->cur_phy_block_ptr&0x3;
}
}
//#ifndef AML_A3
// /*walkaround: manually clear EDID interrupt*/
// hdmi_wr_reg(TX_HDCP_EDID_CONFIG, hdmi_rd_reg(TX_HDCP_EDID_CONFIG) | (1<<1));
// hdmi_wr_reg(TX_HDCP_EDID_CONFIG, hdmi_rd_reg(TX_HDCP_EDID_CONFIG) & ~(1<<1));
// /**/
//#endif
//tasklet_schedule(&EDID_tasklet);
hdmi_wr_only_reg(OTHER_BASE_ADDR + HDMI_OTHER_INTR_STAT_CLR, 1 << 2); //clear EDID rising interrupt in hdmi module
}
if (!((data32 == 1) || (data32 == 2) || (data32 == 4))) {
hdmi_print(ERR, SYS "Unkown HDMI Interrupt Source\n");
hdmi_wr_only_reg(OTHER_BASE_ADDR + HDMI_OTHER_INTR_STAT_CLR, data32); //clear unkown interrupt in hdmi module
}
//#ifdef AML_A3
hdmi_rd_reg(OTHER_BASE_ADDR + HDMI_OTHER_INTR_STAT_CLR); // A read to allow the interrupt cleared in hdmi_module before next action
hdmi_wr_only_reg(OTHER_BASE_ADDR + HDMI_OTHER_INTR_STAT_CLR, 0xf); //clear HPD falling interrupt in hdmi module
//#endif
//aml_write_reg32(P_SYS_CPU_0_IRQ_IN1_INTR_STAT_CLR, 1 << 25); //clear hdmi_tx interrupt
return IRQ_HANDLED;
}
#endif
/*
* mode: 1 means Progressive; 0 means interlaced
*/
static void enc_vpu_bridge_reset(int mode)
{
unsigned int wr_clk = 0;
printk("%s[%d]\n", __func__, __LINE__);
wr_clk = (aml_read_reg32(P_VPU_HDMI_SETTING) & 0xf00) >> 8;
if(mode) {
aml_write_reg32(P_ENCP_VIDEO_EN, 0);
aml_set_reg32_bits(P_VPU_HDMI_SETTING, 0, 0, 2); // [ 0] src_sel_enci: Disable ENCP output to HDMI
aml_set_reg32_bits(P_VPU_HDMI_SETTING, 0, 8, 4); // [ 0] src_sel_enci: Disable ENCP output to HDMI
mdelay(1);
aml_write_reg32(P_ENCP_VIDEO_EN, 1);
mdelay(1);
aml_set_reg32_bits(P_VPU_HDMI_SETTING, wr_clk, 8, 4);
mdelay(1);
aml_set_reg32_bits(P_VPU_HDMI_SETTING, 2, 0, 2); // [ 0] src_sel_enci: Enable ENCP output to HDMI
} else {
aml_write_reg32(P_ENCI_VIDEO_EN, 0);
aml_set_reg32_bits(P_VPU_HDMI_SETTING, 0, 0, 2); // [ 0] src_sel_enci: Disable ENCI output to HDMI
aml_set_reg32_bits(P_VPU_HDMI_SETTING, 0, 8, 4); // [ 0] src_sel_enci: Disable ENCP output to HDMI
mdelay(1);
aml_write_reg32(P_ENCI_VIDEO_EN, 1);
mdelay(1);
aml_set_reg32_bits(P_VPU_HDMI_SETTING, wr_clk, 8, 4);
mdelay(1);
aml_set_reg32_bits(P_VPU_HDMI_SETTING, 1, 0, 2); // [ 0] src_sel_enci: Enable ENCI output to HDMI
}
}
static void hdmi_tvenc1080i_set(Hdmi_tx_video_para_t* param)
{
unsigned long VFIFO2VD_TO_HDMI_LATENCY = 2; // Annie 01Sep2011: Change value from 3 to 2, due to video encoder path delay change.
unsigned long TOTAL_PIXELS, PIXEL_REPEAT_HDMI, PIXEL_REPEAT_VENC, ACTIVE_PIXELS;
unsigned FRONT_PORCH = 88, HSYNC_PIXELS, ACTIVE_LINES = 0, INTERLACE_MODE, TOTAL_LINES, SOF_LINES, VSYNC_LINES;
unsigned LINES_F0, LINES_F1 = 563,BACK_PORCH, EOF_LINES = 2, TOTAL_FRAMES;
unsigned long total_pixels_venc ;
unsigned long active_pixels_venc;
unsigned long front_porch_venc ;
unsigned long hsync_pixels_venc ;
unsigned long de_h_begin, de_h_end;
unsigned long de_v_begin_even, de_v_end_even, de_v_begin_odd, de_v_end_odd;
unsigned long hs_begin, hs_end;
unsigned long vs_adjust;
unsigned long vs_bline_evn, vs_eline_evn, vs_bline_odd, vs_eline_odd;
unsigned long vso_begin_evn, vso_begin_odd;
if(param->VIC==HDMI_1080i60){
INTERLACE_MODE = 1;
PIXEL_REPEAT_VENC = 1;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI)); // Number of active pixels per line.
ACTIVE_LINES = (1080/(1+INTERLACE_MODE)); // Number of active lines per field.
LINES_F0 = 562;
LINES_F1 = 563;
FRONT_PORCH = 88;
HSYNC_PIXELS = 44;
BACK_PORCH = 148;
EOF_LINES = 2;
VSYNC_LINES = 5;
SOF_LINES = 15;
TOTAL_FRAMES = 4;
}
else if(param->VIC==HDMI_1080i50){
INTERLACE_MODE = 1;
PIXEL_REPEAT_VENC = 1;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI)); // Number of active pixels per line.
ACTIVE_LINES = (1080/(1+INTERLACE_MODE)); // Number of active lines per field.
LINES_F0 = 562;
LINES_F1 = 563;
FRONT_PORCH = 528;
HSYNC_PIXELS = 44;
BACK_PORCH = 148;
EOF_LINES = 2;
VSYNC_LINES = 5;
SOF_LINES = 15;
TOTAL_FRAMES = 4;
}
TOTAL_PIXELS =(FRONT_PORCH+HSYNC_PIXELS+BACK_PORCH+ACTIVE_PIXELS); // Number of total pixels per line.
TOTAL_LINES =(LINES_F0+(LINES_F1*INTERLACE_MODE)); // Number of total lines per frame.
total_pixels_venc = (TOTAL_PIXELS / (1+PIXEL_REPEAT_HDMI)) * (1+PIXEL_REPEAT_VENC); // 2200 / 1 * 2 = 4400
active_pixels_venc= (ACTIVE_PIXELS / (1+PIXEL_REPEAT_HDMI)) * (1+PIXEL_REPEAT_VENC); // 1920 / 1 * 2 = 3840
front_porch_venc = (FRONT_PORCH / (1+PIXEL_REPEAT_HDMI)) * (1+PIXEL_REPEAT_VENC); // 88 / 1 * 2 = 176
hsync_pixels_venc = (HSYNC_PIXELS / (1+PIXEL_REPEAT_HDMI)) * (1+PIXEL_REPEAT_VENC); // 44 / 1 * 2 = 88
aml_write_reg32(P_ENCP_VIDEO_MODE, aml_read_reg32(P_ENCP_VIDEO_MODE)|(1<<14)); // cfg_de_v = 1
// Program DE timing
de_h_begin = modulo(aml_read_reg32(P_ENCP_VIDEO_HAVON_BEGIN) + VFIFO2VD_TO_HDMI_LATENCY, total_pixels_venc); // (383 + 3) % 4400 = 386
de_h_end = modulo(de_h_begin + active_pixels_venc, total_pixels_venc); // (386 + 3840) % 4400 = 4226
aml_write_reg32(P_ENCP_DE_H_BEGIN, de_h_begin); // 386
aml_write_reg32(P_ENCP_DE_H_END, de_h_end); // 4226
// Program DE timing for even field
de_v_begin_even = aml_read_reg32(P_ENCP_VIDEO_VAVON_BLINE); // 20
de_v_end_even = de_v_begin_even + ACTIVE_LINES; // 20 + 540 = 560
aml_write_reg32(P_ENCP_DE_V_BEGIN_EVEN,de_v_begin_even); // 20
aml_write_reg32(P_ENCP_DE_V_END_EVEN, de_v_end_even); // 560
// Program DE timing for odd field if needed
if (INTERLACE_MODE) {
// Calculate de_v_begin_odd according to enc480p_timing.v:
//wire[10:0] cfg_ofld_vavon_bline = {{7{ofld_vavon_ofst1 [3]}},ofld_vavon_ofst1 [3:0]} + cfg_video_vavon_bline + ofld_line;
de_v_begin_odd = to_signed((aml_read_reg32(P_ENCP_VIDEO_OFLD_VOAV_OFST) & 0xf0)>>4) + de_v_begin_even + (TOTAL_LINES-1)/2; // 1 + 20 + (1125-1)/2 = 583
de_v_end_odd = de_v_begin_odd + ACTIVE_LINES; // 583 + 540 = 1123
aml_write_reg32(P_ENCP_DE_V_BEGIN_ODD, de_v_begin_odd);// 583
aml_write_reg32(P_ENCP_DE_V_END_ODD, de_v_end_odd); // 1123
}
// Program Hsync timing
if (de_h_end + front_porch_venc >= total_pixels_venc) {
hs_begin = de_h_end + front_porch_venc - total_pixels_venc; // 4226 + 176 - 4400 = 2
vs_adjust = 1;
} else {
hs_begin = de_h_end + front_porch_venc;
vs_adjust = 0;
}
hs_end = modulo(hs_begin + hsync_pixels_venc, total_pixels_venc); // (2 + 88) % 4400 = 90
aml_write_reg32(P_ENCP_DVI_HSO_BEGIN, hs_begin); // 2
aml_write_reg32(P_ENCP_DVI_HSO_END, hs_end); // 90
// Program Vsync timing for even field
if (de_v_begin_even >= SOF_LINES + VSYNC_LINES + (1-vs_adjust)) {
vs_bline_evn = de_v_begin_even - SOF_LINES - VSYNC_LINES - (1-vs_adjust); // 20 - 15 - 5 - 0 = 0
} else {
vs_bline_evn = TOTAL_LINES + de_v_begin_even - SOF_LINES - VSYNC_LINES - (1-vs_adjust);
}
vs_eline_evn = modulo(vs_bline_evn + VSYNC_LINES, TOTAL_LINES); // (0 + 5) % 1125 = 5
aml_write_reg32(P_ENCP_DVI_VSO_BLINE_EVN, vs_bline_evn); // 0
aml_write_reg32(P_ENCP_DVI_VSO_ELINE_EVN, vs_eline_evn); // 5
vso_begin_evn = hs_begin; // 2
aml_write_reg32(P_ENCP_DVI_VSO_BEGIN_EVN, vso_begin_evn); // 2
aml_write_reg32(P_ENCP_DVI_VSO_END_EVN, vso_begin_evn); // 2
// Program Vsync timing for odd field if needed
if (INTERLACE_MODE) {
vs_bline_odd = de_v_begin_odd-1 - SOF_LINES - VSYNC_LINES; // 583-1 - 15 - 5 = 562
vs_eline_odd = de_v_begin_odd-1 - SOF_LINES; // 583-1 - 15 = 567
vso_begin_odd = modulo(hs_begin + (total_pixels_venc>>1), total_pixels_venc); // (2 + 4400/2) % 4400 = 2202
aml_write_reg32(P_ENCP_DVI_VSO_BLINE_ODD, vs_bline_odd); // 562
aml_write_reg32(P_ENCP_DVI_VSO_ELINE_ODD, vs_eline_odd); // 567
aml_write_reg32(P_ENCP_DVI_VSO_BEGIN_ODD, vso_begin_odd); // 2202
aml_write_reg32(P_ENCP_DVI_VSO_END_ODD, vso_begin_odd); // 2202
}
// Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.
aml_write_reg32(P_VPU_HDMI_SETTING, (0 << 0) | // [ 0] src_sel_enci
(0 << 1) | // [ 1] src_sel_encp
(HSYNC_POLARITY << 2) | // [ 2] inv_hsync. 1=Invert Hsync polarity.
(VSYNC_POLARITY << 3) | // [ 3] inv_vsync. 1=Invert Vsync polarity.
(0 << 4) | // [ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).
(((TX_INPUT_COLOR_FORMAT==0)?1:0) << 5) | // [ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:
// 0=output CrYCb(BRG);
// 1=output YCbCr(RGB);
// 2=output YCrCb(RBG);
// 3=output CbCrY(GBR);
// 4=output CbYCr(GRB);
// 5=output CrCbY(BGR);
// 6,7=Rsrv.
#ifdef DOUBLE_CLK_720P_1080I
(0 << 8) | // [11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.
#else
(1 << 8) | // [11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.
#endif
(0 <<12) // [15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.
);
aml_set_reg32_bits(P_VPU_HDMI_SETTING, 1, 1, 1); // [ 1] src_sel_encp: Enable ENCP output to HDMI
}
static void hdmi_tvenc480i_set(Hdmi_tx_video_para_t* param)
{
unsigned long VFIFO2VD_TO_HDMI_LATENCY = 1; // Annie 01Sep2011: Change value from 2 to 1, due to video encoder path delay change.
unsigned long TOTAL_PIXELS, PIXEL_REPEAT_HDMI, PIXEL_REPEAT_VENC, ACTIVE_PIXELS;
unsigned FRONT_PORCH = 38, HSYNC_PIXELS = 124, ACTIVE_LINES = 0, INTERLACE_MODE, TOTAL_LINES, SOF_LINES, VSYNC_LINES;
unsigned LINES_F0 = 262, LINES_F1 = 263, BACK_PORCH = 114, EOF_LINES = 2, TOTAL_FRAMES;
unsigned long total_pixels_venc ;
unsigned long active_pixels_venc;
unsigned long front_porch_venc ;
unsigned long hsync_pixels_venc ;
unsigned long de_h_begin, de_h_end;
unsigned long de_v_begin_even, de_v_end_even, de_v_begin_odd, de_v_end_odd;
unsigned long hs_begin, hs_end;
unsigned long vs_adjust;
unsigned long vs_bline_evn, vs_eline_evn, vs_bline_odd, vs_eline_odd;
unsigned long vso_begin_evn, vso_begin_odd;
switch(param->VIC) {
case HDMI_480i60:
case HDMI_480i60_16x9:
case HDMI_480i60_16x9_rpt:
INTERLACE_MODE = 1;
PIXEL_REPEAT_VENC = 1;
PIXEL_REPEAT_HDMI = 1;
ACTIVE_PIXELS = (720*(1+PIXEL_REPEAT_HDMI)); // Number of active pixels per line.
ACTIVE_LINES = (480/(1+INTERLACE_MODE)); // Number of active lines per field.
LINES_F0 = 262;
LINES_F1 = 263;
FRONT_PORCH = 38;
HSYNC_PIXELS = 124;
BACK_PORCH = 114;
EOF_LINES = 4;
VSYNC_LINES = 3;
SOF_LINES = 15;
TOTAL_FRAMES = 4;
break;
case HDMI_576i50:
case HDMI_576i50_16x9:
case HDMI_576i50_16x9_rpt:
INTERLACE_MODE = 1;
PIXEL_REPEAT_VENC = 1;
PIXEL_REPEAT_HDMI = 1;
ACTIVE_PIXELS = (720*(1+PIXEL_REPEAT_HDMI)); // Number of active pixels per line.
ACTIVE_LINES = (576/(1+INTERLACE_MODE)); // Number of active lines per field.
LINES_F0 = 312;
LINES_F1 = 313;
FRONT_PORCH = 24;
HSYNC_PIXELS = 126;
BACK_PORCH = 138;
EOF_LINES = 2;
VSYNC_LINES = 3;
SOF_LINES = 19;
TOTAL_FRAMES = 4;
break;
default:
break;
}
TOTAL_PIXELS =(FRONT_PORCH+HSYNC_PIXELS+BACK_PORCH+ACTIVE_PIXELS); // Number of total pixels per line.
TOTAL_LINES =(LINES_F0+(LINES_F1*INTERLACE_MODE)); // Number of total lines per frame.
total_pixels_venc = (TOTAL_PIXELS / (1+PIXEL_REPEAT_HDMI)) * (1+PIXEL_REPEAT_VENC); // 1716 / 2 * 2 = 1716
active_pixels_venc= (ACTIVE_PIXELS / (1+PIXEL_REPEAT_HDMI)) * (1+PIXEL_REPEAT_VENC); // 1440 / 2 * 2 = 1440
front_porch_venc = (FRONT_PORCH / (1+PIXEL_REPEAT_HDMI)) * (1+PIXEL_REPEAT_VENC); // 38 / 2 * 2 = 38
hsync_pixels_venc = (HSYNC_PIXELS / (1+PIXEL_REPEAT_HDMI)) * (1+PIXEL_REPEAT_VENC); // 124 / 2 * 2 = 124
// Annie 01Sep2011: Comment out the following 2 lines. Because ENCP is not used for 480i and 576i.
//Wr(ENCP_VIDEO_MODE,Rd(ENCP_VIDEO_MODE)|(1<<14)); // cfg_de_v = 1
// Program DE timing
// Annie 01Sep2011: for 480/576i, replace VFIFO2VD_PIXEL_START with ENCI_VFIFO2VD_PIXEL_START.
de_h_begin = modulo(aml_read_reg32(P_ENCI_VFIFO2VD_PIXEL_START) + VFIFO2VD_TO_HDMI_LATENCY, total_pixels_venc); // (233 + 2) % 1716 = 235
de_h_end = modulo(de_h_begin + active_pixels_venc, total_pixels_venc); // (235 + 1440) % 1716 = 1675
aml_write_reg32(P_ENCI_DE_H_BEGIN, de_h_begin); // 235
aml_write_reg32(P_ENCI_DE_H_END, de_h_end); // 1675
// Annie 01Sep2011: for 480/576i, replace VFIFO2VD_LINE_TOP/BOT_START with ENCI_VFIFO2VD_LINE_TOP/BOT_START.
de_v_begin_even = aml_read_reg32(P_ENCI_VFIFO2VD_LINE_TOP_START); // 17
de_v_end_even = de_v_begin_even + ACTIVE_LINES; // 17 + 240 = 257
de_v_begin_odd = aml_read_reg32(P_ENCI_VFIFO2VD_LINE_BOT_START); // 18
de_v_end_odd = de_v_begin_odd + ACTIVE_LINES; // 18 + 480/2 = 258
aml_write_reg32(P_ENCI_DE_V_BEGIN_EVEN,de_v_begin_even); // 17
aml_write_reg32(P_ENCI_DE_V_END_EVEN, de_v_end_even); // 257
aml_write_reg32(P_ENCI_DE_V_BEGIN_ODD, de_v_begin_odd); // 18
aml_write_reg32(P_ENCI_DE_V_END_ODD, de_v_end_odd); // 258
// Program Hsync timing
if (de_h_end + front_porch_venc >= total_pixels_venc) {
hs_begin = de_h_end + front_porch_venc - total_pixels_venc;
vs_adjust = 1;
} else {
hs_begin = de_h_end + front_porch_venc; // 1675 + 38 = 1713
vs_adjust = 0;
}
hs_end = modulo(hs_begin + hsync_pixels_venc, total_pixels_venc); // (1713 + 124) % 1716 = 121
aml_write_reg32(P_ENCI_DVI_HSO_BEGIN, hs_begin); // 1713
aml_write_reg32(P_ENCI_DVI_HSO_END, hs_end); // 121
// Program Vsync timing for even field
if (de_v_end_odd-1 + EOF_LINES + vs_adjust >= LINES_F1) {
vs_bline_evn = de_v_end_odd-1 + EOF_LINES + vs_adjust - LINES_F1;
vs_eline_evn = vs_bline_evn + VSYNC_LINES;
aml_write_reg32(P_ENCI_DVI_VSO_BLINE_EVN, vs_bline_evn);
//vso_bline_evn_reg_wr_cnt ++;
aml_write_reg32(P_ENCI_DVI_VSO_ELINE_EVN, vs_eline_evn);
//vso_eline_evn_reg_wr_cnt ++;
aml_write_reg32(P_ENCI_DVI_VSO_BEGIN_EVN, hs_begin);
aml_write_reg32(P_ENCI_DVI_VSO_END_EVN, hs_begin);
} else {
vs_bline_odd = de_v_end_odd-1 + EOF_LINES + vs_adjust; // 258-1 + 4 + 0 = 261
aml_write_reg32(P_ENCI_DVI_VSO_BLINE_ODD, vs_bline_odd); // 261
//vso_bline_odd_reg_wr_cnt ++;
aml_write_reg32(P_ENCI_DVI_VSO_BEGIN_ODD, hs_begin); // 1713
if (vs_bline_odd + VSYNC_LINES >= LINES_F1) {
vs_eline_evn = vs_bline_odd + VSYNC_LINES - LINES_F1; // 261 + 3 - 263 = 1
aml_write_reg32(P_ENCI_DVI_VSO_ELINE_EVN, vs_eline_evn); // 1
//vso_eline_evn_reg_wr_cnt ++;
aml_write_reg32(P_ENCI_DVI_VSO_END_EVN, hs_begin); // 1713
} else {
vs_eline_odd = vs_bline_odd + VSYNC_LINES;
aml_write_reg32(P_ENCI_DVI_VSO_ELINE_ODD, vs_eline_odd);
//vso_eline_odd_reg_wr_cnt ++;
aml_write_reg32(P_ENCI_DVI_VSO_END_ODD, hs_begin);
}
}
// Program Vsync timing for odd field
if (de_v_end_even-1 + EOF_LINES + 1 >= LINES_F0) {
vs_bline_odd = de_v_end_even-1 + EOF_LINES + 1 - LINES_F0;
vs_eline_odd = vs_bline_odd + VSYNC_LINES;
aml_write_reg32(P_ENCI_DVI_VSO_BLINE_ODD, vs_bline_odd);
//vso_bline_odd_reg_wr_cnt ++;
aml_write_reg32(P_ENCI_DVI_VSO_ELINE_ODD, vs_eline_odd);
//vso_eline_odd_reg_wr_cnt ++;
vso_begin_odd = modulo(hs_begin + (total_pixels_venc>>1), total_pixels_venc);
aml_write_reg32(P_ENCI_DVI_VSO_BEGIN_ODD, vso_begin_odd);
aml_write_reg32(P_ENCI_DVI_VSO_END_ODD, vso_begin_odd);
} else {
vs_bline_evn = de_v_end_even-1 + EOF_LINES + 1; // 257-1 + 4 + 1 = 261
aml_write_reg32(P_ENCI_DVI_VSO_BLINE_EVN, vs_bline_evn); // 261
//vso_bline_evn_reg_wr_cnt ++;
vso_begin_evn = modulo(hs_begin + (total_pixels_venc>>1), total_pixels_venc); // (1713 + 1716/2) % 1716 = 855
aml_write_reg32(P_ENCI_DVI_VSO_BEGIN_EVN, vso_begin_evn); // 855
if (vs_bline_evn + VSYNC_LINES >= LINES_F0) {
vs_eline_odd = vs_bline_evn + VSYNC_LINES - LINES_F0; // 261 + 3 - 262 = 2
aml_write_reg32(P_ENCI_DVI_VSO_ELINE_ODD, vs_eline_odd); // 2
//vso_eline_odd_reg_wr_cnt ++;
aml_write_reg32(P_ENCI_DVI_VSO_END_ODD, vso_begin_evn); // 855
} else {
vs_eline_evn = vs_bline_evn + VSYNC_LINES;
aml_write_reg32(P_ENCI_DVI_VSO_ELINE_EVN, vs_eline_evn);
//vso_eline_evn_reg_wr_cnt ++;
aml_write_reg32(P_ENCI_DVI_VSO_END_EVN, vso_begin_evn);
}
}
aml_set_reg32_bits(P_HHI_GCLK_OTHER, 1, 8, 1); // Enable VENCI gate
// Check if there are duplicate or missing timing settings
//if ((vso_bline_evn_reg_wr_cnt != 1) || (vso_bline_odd_reg_wr_cnt != 1) ||
// (vso_eline_evn_reg_wr_cnt != 1) || (vso_eline_odd_reg_wr_cnt != 1)) {
//stimulus_print("[TEST.C] Error: Multiple or missing timing settings on reg ENCI_DVI_VSO_B(E)LINE_EVN(ODD)!\n");
//stimulus_finish_fail(1);
//}
// Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.
aml_write_reg32(P_VPU_HDMI_SETTING, (0 << 0) | // [ 0] src_sel_enci
(0 << 1) | // [ 1] src_sel_encp
(0 << 2) | // [ 2] inv_hsync. 1=Invert Hsync polarity.
(0 << 3) | // [ 3] inv_vsync. 1=Invert Vsync polarity.
(0 << 4) | // [ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).
(((TX_INPUT_COLOR_FORMAT==0)?1:0) << 5) | // [ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:
// 0=output CrYCb(BRG);
// 1=output YCbCr(RGB);
// 2=output YCrCb(RBG);
// 3=output CbCrY(GBR);
// 4=output CbYCr(GRB);
// 5=output CrCbY(BGR);
// 6,7=Rsrv.
(1 << 8) | // [11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.
(1 <<12) // [15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.
);
if((param->VIC == HDMI_480i60_16x9_rpt) || (param->VIC == HDMI_576i50_16x9_rpt)) {
aml_set_reg32_bits(P_VPU_HDMI_SETTING, 3, 12, 4);
}
aml_set_reg32_bits(P_VPU_HDMI_SETTING, 1, 0, 1); // [ 0] src_sel_enci: Enable ENCI output to HDMI
}
static void hdmi_tvenc_set(Hdmi_tx_video_para_t *param)
{
unsigned long VFIFO2VD_TO_HDMI_LATENCY = 2; // Annie 01Sep2011: Change value from 3 to 2, due to video encoder path delay change.
unsigned long TOTAL_PIXELS, PIXEL_REPEAT_HDMI, PIXEL_REPEAT_VENC, ACTIVE_PIXELS;
unsigned FRONT_PORCH, HSYNC_PIXELS, ACTIVE_LINES, INTERLACE_MODE, TOTAL_LINES, SOF_LINES, VSYNC_LINES;
unsigned LINES_F0, LINES_F1,BACK_PORCH, EOF_LINES, TOTAL_FRAMES;
unsigned long total_pixels_venc ;
unsigned long active_pixels_venc;
unsigned long front_porch_venc ;
unsigned long hsync_pixels_venc ;
unsigned long de_h_begin, de_h_end;
unsigned long de_v_begin_even, de_v_end_even, de_v_begin_odd, de_v_end_odd;
unsigned long hs_begin, hs_end;
unsigned long vs_adjust;
unsigned long vs_bline_evn, vs_eline_evn, vs_bline_odd, vs_eline_odd;
unsigned long vso_begin_evn, vso_begin_odd;
switch(param->VIC) {
case HDMIV_800x480p60hz:
INTERLACE_MODE = 0;
PIXEL_REPEAT_VENC = 0;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = 800;
ACTIVE_LINES = 480;
LINES_F0 = 500;
LINES_F1 = 500;
FRONT_PORCH = 24;
HSYNC_PIXELS = 72;
BACK_PORCH = 96;
EOF_LINES = 3;
VSYNC_LINES = 7;
SOF_LINES = 10;
TOTAL_FRAMES = 4;
break;
case HDMIV_800x600p60hz:
case HDMIV_800x600p75hz:
INTERLACE_MODE = 0;
PIXEL_REPEAT_VENC = 0;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = 800;
ACTIVE_LINES = 600;
LINES_F0 = 628;
LINES_F1 = 628;
FRONT_PORCH = 40;
HSYNC_PIXELS = 128;
BACK_PORCH = 88;
EOF_LINES = 1;
VSYNC_LINES = 4;
SOF_LINES = 23;
TOTAL_FRAMES = 4;
break;
case HDMIV_1024x600p60hz:
INTERLACE_MODE = 0;
PIXEL_REPEAT_VENC = 0;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = 1024;
ACTIVE_LINES = 600;
LINES_F0 = 638;
LINES_F1 = 638;
FRONT_PORCH = 24;
HSYNC_PIXELS = 136;
BACK_PORCH = 160;
EOF_LINES = 3;
VSYNC_LINES = 6;
SOF_LINES = 29;
TOTAL_FRAMES = 4;
break;
case HDMIV_1024x768p60hz:
INTERLACE_MODE = 0;
PIXEL_REPEAT_VENC = 0;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = 1024;
ACTIVE_LINES = 768;
LINES_F0 = 806;
LINES_F1 = 806;
FRONT_PORCH = 24;
HSYNC_PIXELS = 136;
BACK_PORCH = 160;
EOF_LINES = 3;
VSYNC_LINES = 6;
SOF_LINES = 29;
TOTAL_FRAMES = 4;
break;
case HDMIV_1024x768p75hz:
INTERLACE_MODE = 0;
PIXEL_REPEAT_VENC = 0;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = (1024*(1+PIXEL_REPEAT_HDMI)); // Number of active pixels per line.
ACTIVE_LINES = (768/(1+INTERLACE_MODE)); // Number of active lines per field.
LINES_F0 = 806;
LINES_F1 = 806;
FRONT_PORCH = 24;
HSYNC_PIXELS = 136;
BACK_PORCH = 160;
EOF_LINES = 3;
VSYNC_LINES = 6;
SOF_LINES = 29;
break;
case HDMIV_1280x1024p75hz:
INTERLACE_MODE = 0;
PIXEL_REPEAT_VENC = 0;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = (1280*(1+PIXEL_REPEAT_HDMI)); // Number of active pixels per line.
ACTIVE_LINES = (1024/(1+INTERLACE_MODE)); // Number of active lines per field.
LINES_F0 = 1066;
LINES_F1 = 1066;
FRONT_PORCH = 48;
HSYNC_PIXELS = 112;
BACK_PORCH = 248;
EOF_LINES = 1;
VSYNC_LINES = 3;
SOF_LINES = 38;
TOTAL_FRAMES = 4;
break;
case HDMIV_1280x800p60hz:
INTERLACE_MODE = 0;
PIXEL_REPEAT_VENC = 0;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = 1280;
ACTIVE_LINES = 800;
LINES_F0 = 823;
LINES_F1 = 823;
FRONT_PORCH = 48;
HSYNC_PIXELS = 32;
BACK_PORCH = 80;
EOF_LINES = 3;
VSYNC_LINES = 6;
SOF_LINES = 14;
break;
case HDMIV_1280x1024p60hz:
INTERLACE_MODE = 0;
PIXEL_REPEAT_VENC = 0;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = 1280;
ACTIVE_LINES = 1024;
LINES_F0 = 1066;
LINES_F1 = 1066;
FRONT_PORCH = 48;
HSYNC_PIXELS = 112;
BACK_PORCH = 248;
EOF_LINES = 1;
VSYNC_LINES = 3;
SOF_LINES = 38;
break;
case HDMIV_1360x768p60hz:
INTERLACE_MODE = 0;
PIXEL_REPEAT_VENC = 0;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = 1360;
ACTIVE_LINES = 768;
LINES_F0 = 795;
LINES_F1 = 795;
FRONT_PORCH = 64;
HSYNC_PIXELS = 112;
BACK_PORCH = 256;
EOF_LINES = 3;
VSYNC_LINES = 6;
SOF_LINES = 18;
TOTAL_FRAMES = 4;
break;
case HDMIV_1366x768p60hz:
INTERLACE_MODE = 0;
PIXEL_REPEAT_VENC = 0;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = 1366;
ACTIVE_LINES = 768;
LINES_F0 = 798;
LINES_F1 = 798;
FRONT_PORCH = 70;
HSYNC_PIXELS = 143;
BACK_PORCH = 213;
EOF_LINES = 3;
VSYNC_LINES = 3;
SOF_LINES = 24;
TOTAL_FRAMES = 4;
break;
case HDMIV_1440x900p60hz:
INTERLACE_MODE = 0;
PIXEL_REPEAT_VENC = 0;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = 1440;
ACTIVE_LINES = 900;
LINES_F0 = 934;
LINES_F1 = 934;
FRONT_PORCH = 80;
HSYNC_PIXELS = 152;
BACK_PORCH = 232;
EOF_LINES = 3;
VSYNC_LINES = 6;
SOF_LINES = 25;
TOTAL_FRAMES = 4;
break;
case HDMIV_1600x900p60hz:
INTERLACE_MODE = 0;
PIXEL_REPEAT_VENC = 0;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = 1600;
ACTIVE_LINES = 900;
LINES_F0 = 1800;
LINES_F1 = 1800;
FRONT_PORCH = 24;
HSYNC_PIXELS = 80;
BACK_PORCH = 96;
EOF_LINES = 1;
VSYNC_LINES = 3;
SOF_LINES = 96;
TOTAL_FRAMES = 4;
break;
case HDMIV_1680x1050p60hz:
INTERLACE_MODE = 0;
PIXEL_REPEAT_VENC = 0;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = 1680;
ACTIVE_LINES = 1050;
LINES_F0 = 1089;
LINES_F1 = 1089;
FRONT_PORCH = 104;
HSYNC_PIXELS = 176;
BACK_PORCH = 280;
EOF_LINES = 3;
VSYNC_LINES = 6;
SOF_LINES = 30;
TOTAL_FRAMES = 4;
break;
case HDMIV_1920x1200p60hz:
INTERLACE_MODE = 0;
PIXEL_REPEAT_VENC = 0;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = 1920;
ACTIVE_LINES = 1200;
LINES_F0 = 1245;
LINES_F1 = 1245;
FRONT_PORCH = 136;
HSYNC_PIXELS = 200;
BACK_PORCH = 336;
EOF_LINES = 3;
VSYNC_LINES = 6;
SOF_LINES = 36;
break;
case HDMI_640x480p60_4x3:
case HDMIV_640x480p75hz:
INTERLACE_MODE = 0;
PIXEL_REPEAT_VENC = 0;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = (640*(1+PIXEL_REPEAT_HDMI)); // Number of active pixels per line.
ACTIVE_LINES = (480/(1+INTERLACE_MODE)); // Number of active lines per field.
LINES_F0 = 525;
LINES_F1 = 525;
FRONT_PORCH = 16;
HSYNC_PIXELS = 96;
BACK_PORCH = 48;
EOF_LINES = 20;
VSYNC_LINES = 2;
SOF_LINES = 33;
TOTAL_FRAMES = 4;
break;
case HDMI_480p60:
case HDMI_480p60_16x9:
case HDMI_480p60_16x9_rpt:
INTERLACE_MODE = 0;
PIXEL_REPEAT_VENC = 1;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = (720*(1+PIXEL_REPEAT_HDMI)); // Number of active pixels per line.
ACTIVE_LINES = (480/(1+INTERLACE_MODE)); // Number of active lines per field.
LINES_F0 = 525;
LINES_F1 = 525;
FRONT_PORCH = 16;
HSYNC_PIXELS = 62;
BACK_PORCH = 60;
EOF_LINES = 9;
VSYNC_LINES = 6;
SOF_LINES = 30;
TOTAL_FRAMES = 4;
break;
case HDMI_576p50:
case HDMI_576p50_16x9:
case HDMI_576p50_16x9_rpt:
INTERLACE_MODE = 0;
PIXEL_REPEAT_VENC = 1;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = (720*(1+PIXEL_REPEAT_HDMI)); // Number of active pixels per line.
ACTIVE_LINES = (576/(1+INTERLACE_MODE)); // Number of active lines per field.
LINES_F0 = 625;
LINES_F1 = 625;
FRONT_PORCH = 12;
HSYNC_PIXELS = 64;
BACK_PORCH = 68;
EOF_LINES = 5;
VSYNC_LINES = 5;
SOF_LINES = 39;
TOTAL_FRAMES = 4;
break;
case HDMI_720p60:
INTERLACE_MODE = 0;
PIXEL_REPEAT_VENC = 1;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = (1280*(1+PIXEL_REPEAT_HDMI)); // Number of active pixels per line.
ACTIVE_LINES = (720/(1+INTERLACE_MODE)); // Number of active lines per field.
LINES_F0 = 750;
LINES_F1 = 750;
FRONT_PORCH = 110;
HSYNC_PIXELS = 40;
BACK_PORCH = 220;
EOF_LINES = 5;
VSYNC_LINES = 5;
SOF_LINES = 20;
TOTAL_FRAMES = 4;
break;
case HDMI_720p50:
INTERLACE_MODE = 0;
PIXEL_REPEAT_VENC = 1;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = (1280*(1+PIXEL_REPEAT_HDMI)); // Number of active pixels per line.
ACTIVE_LINES = (720/(1+INTERLACE_MODE)); // Number of active lines per field.
LINES_F0 = 750;
LINES_F1 = 750;
FRONT_PORCH = 440;
HSYNC_PIXELS = 40;
BACK_PORCH = 220;
EOF_LINES = 5;
VSYNC_LINES = 5;
SOF_LINES = 20;
TOTAL_FRAMES = 4;
break;
case HDMI_1080p50:
INTERLACE_MODE = 0;
PIXEL_REPEAT_VENC = 0;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI)); // Number of active pixels per line.
ACTIVE_LINES = (1080/(1+INTERLACE_MODE)); // Number of active lines per field.
LINES_F0 = 1125;
LINES_F1 = 1125;
FRONT_PORCH = 528;
HSYNC_PIXELS = 44;
BACK_PORCH = 148;
EOF_LINES = 4;
VSYNC_LINES = 5;
SOF_LINES = 36;
TOTAL_FRAMES = 4;
break;
case HDMI_1080p24:
INTERLACE_MODE = 0;
PIXEL_REPEAT_VENC = 0;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI)); // Number of active pixels per line.
ACTIVE_LINES = (1080/(1+INTERLACE_MODE)); // Number of active lines per field.
LINES_F0 = 1125;
LINES_F1 = 1125;