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hwdocs: Convert NV01 top-level mmio list to .. space::
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mwkmwkmwk committed Feb 3, 2014
1 parent 0ac8717 commit 803b0b0
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Showing 14 changed files with 532 additions and 409 deletions.
16 changes: 8 additions & 8 deletions hwdocs/bus/nv01-prm.rst
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Expand Up @@ -13,20 +13,20 @@ Introduction
.. todo:: figure out what the fuck this engine does .. todo:: figure out what the fuck this engine does




.. _nv01-prm-mmio:

The MMIO registers The MMIO registers
================== ==================


.. todo:: write me .. space:: 8 nv01-prm 0x8000 VGA compatibility control


.. todo:: write me


.. _nv01-prmio-mmio:


The IO ports The IO ports
============ ============


.. todo:: write me .. space:: 8 nv01-prmio 0x1000 VGA and ISA sound compat IO port access

.. todo:: write me




.. _nv01-vga-regs: .. _nv01-vga-regs:
Expand All @@ -53,12 +53,12 @@ SR 0x04: MEMORY_CONTROL
- 1: chained mode - 1: chained mode




.. _nv01-prmfb-mmio:

The VGA memory window The VGA memory window
===================== =====================


.. todo:: write me .. space:: 8 nv01-prmfb 0x20000 aliases VGA memory window

.. todo:: write me




.. _nv01-prm-intr: .. _nv01-prm-intr:
Expand Down
64 changes: 34 additions & 30 deletions hwdocs/bus/pbus.rst
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Expand Up @@ -26,36 +26,40 @@ In addition to this range, PBUS also owns :ref:`PEEPHOLE <peephole-mmio>` and


The registers in the PBUS area are: The registers in the PBUS area are:


============= ========= =============== .. space:: 8 pbus 0x1000 bus control
Range Variants Description
============= ========= =============== .. todo:: connect
001000:0010f0 NV04- :ref:`DEBUG registers <pbus-mmio-debug>`
0010f0:0010f4 NV11:NV50 :ref:`PWM - PWM generators <pbus-mmio-pwm>` ============= ========= ===============
001100:001200 NV03- :ref:`interrupts <pbus-mmio-intr>` Range Variants Description
001200:001208 NV04:NV50 :ref:`ROM control <prom-mmio-rom-timings>` ============= ========= ===============
001300:001380 NV17:NV20 :ref:`HWSQ - hardware sequencer <hwsq-mmio>` 001000:0010f0 NV04- :ref:`DEBUG registers <pbus-mmio-debug>`
NV25:NVC0 0010f0:0010f4 NV11:NV50 :ref:`PWM - PWM generators <pbus-mmio-pwm>`
001380:001400 NV41:NV50 :ref:`VGA_STACK <pbus-mmio-vga-stack>` 001100:001200 NV03- :ref:`interrupts <pbus-mmio-intr>`
001400:001500 NV17:NV20 :ref:`HWSQ - hardware sequencer <hwsq-mmio>` 001200:001208 NV04:NV50 :ref:`ROM control <prom-mmio-rom-timings>`
NV25:NVC0 001300:001380 NV17:NV20 :ref:`HWSQ - hardware sequencer <hwsq-mmio>`
001500:001540 ??? :ref:`DEBUG registers <pbus-mmio-debug>` NV25:NVC0
001540:001550 NV40:NVC0 HWUNITS - enabling/disabling optional hardware subunits [see below] 001380:001400 NV41:NV50 :ref:`VGA_STACK <pbus-mmio-vga-stack>`
00155c:001578 NV30:NV84 :ref:`PEEPHOLE - indirect memory access <peephole-mmio>` 001400:001500 NV17:NV20 :ref:`HWSQ - hardware sequencer <hwsq-mmio>`
001578:001580 NV41:NVC0 :ref:`HWSQ - hardware sequencer <hwsq-mmio>` NV25:NVC0
001580:0015a0 NV17:NV20 CLOCK_GATE - clock gating registers [see below] 001500:001540 ??? :ref:`DEBUG registers <pbus-mmio-debug>`
NV25:NVC0 001540:001550 NV40:NVC0 HWUNITS - enabling/disabling optional hardware subunits [see below]
0015b0:0015c0 NV43:NV50 :ref:`THERM - thermal sensor <nv43-therm-mmio>` 00155c:001578 NV30:NV84 :ref:`PEEPHOLE - indirect memory access <peephole-mmio>`
0015f4:001604 NV41:NV50 :ref:`PWM - PWM generators <pbus-mmio-pwm>` 001578:001580 NV41:NVC0 :ref:`HWSQ - hardware sequencer <hwsq-mmio>`
001700:001800 TC :ref:`HOST_MEM - host memory access setup <pbus-mmio-nv44-host-mem>` 001580:0015a0 NV17:NV20 CLOCK_GATE - clock gating registers [see below]
001700:001800 NV50:NVC0 :ref:`HOST_MEM - host memory access setup <pbus-mmio-nv50-host-mem>` NV25:NVC0
001700:001800 NVC0- :ref:`HOST_MEM - host memory access setup <pbus-mmio-nvc0-host-mem>` 0015b0:0015c0 NV43:NV50 :ref:`THERM - thermal sensor <nv43-therm-mmio>`
001800:001a00 NV01:NV50 :ref:`PCI - PCI configuration space <pbus-mmio-pci>` 0015f4:001604 NV41:NV50 :ref:`PWM - PWM generators <pbus-mmio-pwm>`
001900:001980 NV50:NVC0 :ref:`REMAP - BAR1 remapping circuitry <pbus-mmio-nv50-remap>` 001700:001800 TC :ref:`HOST_MEM - host memory access setup <pbus-mmio-nv44-host-mem>`
001980:001a00 NV50:NVC0 :ref:`P2P - NV50 P2P slave <pbus-mmio-nv50-p2p>` 001700:001800 NV50:NVC0 :ref:`HOST_MEM - host memory access setup <pbus-mmio-nv50-host-mem>`
001a14 NVA3:NVC0 :ref:`IBUS_TIMEOUT - controls timeout length for accessing MMIO via IBUS <pbus-mmio-ibus-timeout>` 001700:001800 NVC0- :ref:`HOST_MEM - host memory access setup <pbus-mmio-nvc0-host-mem>`
============= ========= =============== 001800:001a00 NV01:NV50 :ref:`PCI - PCI configuration space <pbus-mmio-pci>`

001900:001980 NV50:NVC0 :ref:`REMAP - BAR1 remapping circuitry <pbus-mmio-nv50-remap>`
.. todo:: loads and loads of unknown registers not shown 001980:001a00 NV50:NVC0 :ref:`P2P - NV50 P2P slave <pbus-mmio-nv50-p2p>`
001a14 NVA3:NVC0 :ref:`IBUS_TIMEOUT - controls timeout length for accessing MMIO via IBUS <pbus-mmio-ibus-timeout>`
============= ========= ===============

.. todo:: loads and loads of unknown registers not shown




.. _pbus-mmio-debug: .. _pbus-mmio-debug:
Expand Down
6 changes: 3 additions & 3 deletions hwdocs/display/nv01/pdac.rst
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Expand Up @@ -15,12 +15,12 @@ Introduction
.. todo:: write me .. todo:: write me




.. _nv01-pdac-mmio:

The MMIO registers The MMIO registers
================== ==================


.. todo:: write me .. space:: 8 nv01-pdac 0x1000 DAC control

.. todo:: write me




The DAC registers The DAC registers
Expand Down
6 changes: 3 additions & 3 deletions hwdocs/display/nv01/pfb.rst
View file
Expand Up @@ -15,12 +15,12 @@ Introduction
.. todo:: write me .. todo:: write me




.. _nv01-pfb-mmio:

The MMIO registers The MMIO registers
================== ==================


.. todo:: write me .. space:: 8 nv01-pfb 0x1000 VRAM and video output control

.. todo:: write me




.. _nv01-pfb-mmio-vram-size: .. _nv01-pfb-mmio-vram-size:
Expand Down
7 changes: 4 additions & 3 deletions hwdocs/envy.py
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Expand Up @@ -60,11 +60,13 @@ def run(self):
node.name = obj.name node.name = obj.name
obj.docname = self.env.docname obj.docname = self.env.docname


objects = self.env.domaindata['envy']['objects']

signode = addnodes.desc_signature('', '') signode = addnodes.desc_signature('', '')
signode['first'] = True signode['first'] = True
node.append(signode) node.append(signode)
self.make_signature(obj, signode) self.make_signature(obj, signode)
if not noindex: if not noindex and self.name not in objects:
# only add target and index entry if this is the first # only add target and index entry if this is the first
# description of the object with this name in this desc block # description of the object with this name in this desc block
#self.add_target_and_index(self.name, sig, signode) #self.add_target_and_index(self.name, sig, signode)
Expand All @@ -81,7 +83,6 @@ def run(self):


node.append(uplink_placeholder(self.name)) node.append(uplink_placeholder(self.name))


objects = self.env.domaindata['envy']['objects']
if self.name in objects: if self.name in objects:
other = objects[self.name] other = objects[self.name]
self.state_machine.reporter.warning('duplicate object {}, other instance in {}'.format(self.name, self.env.doc2path(other.docname))) self.state_machine.reporter.warning('duplicate object {}, other instance in {}'.format(self.name, self.env.doc2path(other.docname)))
Expand Down Expand Up @@ -231,7 +232,7 @@ def envy_resolve(app, doctree, fromdocname):
entry = nodes.entry() entry = nodes.entry()
para = nodes.paragraph() para = nodes.paragraph()
entry += para entry += para
para += make_refnode(app.builder, fromdocname, child.docname, child.iname + '-' + child.name, nodes.Text(child.brief, child.brief), obj.brief) para += make_refnode(app.builder, fromdocname, child.docname, child.iname + '-' + child.name, nodes.Text(child.brief, child.brief), child.brief)
row += entry row += entry
tbody += row tbody += row
holder.replace_self([table]) holder.replace_self([table])
Expand Down
118 changes: 65 additions & 53 deletions hwdocs/fifo/nv01-pfifo.rst
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Expand Up @@ -42,59 +42,63 @@ otherwise affect PFIFO]:
The MMIO registers The MMIO registers
================== ==================


=============== ===================== ============ .. space:: 8 nv01-pfifo 0x2000 MMIO-mapped FIFO submission to PGRAPH
Address Name Description
=============== ===================== ============ .. todo:: connect
002040 WAIT_RETRY ??? [XXX]
002080 CACHE_ERROR puller error status =============== ===================== ============
002100 INTR interrupt status / acknowledge Address Name Description
002140 INTR_EN interrupt enable =============== ===================== ============
002200 CONFIG pusher configuration 002040 WAIT_RETRY ??? [XXX]
002210 [3]_ RAMHT RAMHT pointer and configuration 002080 CACHE_ERROR puller error status
002214 [3]_ RAMFC RAMFC pointer 002100 INTR interrupt status / acknowledge
002218 [3]_ RAMRO RAMRO pointer and configuration 002140 INTR_EN interrupt enable
002400 RUNOUT_STATUS RAMRO status 002200 CONFIG pusher configuration
002410 RUNOUT_PUT RAMRO write pointer 002210 [3]_ RAMHT RAMHT pointer and configuration
002420 RUNOUT_GET RAMRO read pointer 002214 [3]_ RAMFC RAMFC pointer
002500 CACHES_REASSIGN CACHE channel switch control 002218 [3]_ RAMRO RAMRO pointer and configuration
002800 DEVICE PGRAPH engine status ? 002400 RUNOUT_STATUS RAMRO status
003000 CACHE0.PUSH_ACCESS CACHE0 pusher enable 002410 RUNOUT_PUT RAMRO write pointer
003010 [1]_ CACHE0.CHID CACHE0 channel ID 002420 RUNOUT_GET RAMRO read pointer
003020 [1]_ CACHE0.STATUS CACHE0 status 002500 CACHES_REASSIGN CACHE channel switch control
003030 [1]_ CACHE0.PUT CACHE0 pusher write pointer 002800 DEVICE PGRAPH engine status ?
003004 [3]_ CACHE0.CHID CACHE0 channel ID 003000 CACHE0.PUSH_ACCESS CACHE0 pusher enable
003010 [3]_ CACHE0.PUT CACHE0 pusher write pointer 003010 [1]_ CACHE0.CHID CACHE0 channel ID
003014 [3]_ CACHE0.STATUS CACHE0 status 003020 [1]_ CACHE0.STATUS CACHE0 status
003040 CACHE0.PULL_CTRL CACHE0 puller control 003030 [1]_ CACHE0.PUT CACHE0 pusher write pointer
003050 [1]_ CACHE0.PULL_STATE CACHE0 puller state 003004 [3]_ CACHE0.CHID CACHE0 channel ID
003070 CACHE0.GET CACHE0 puller read pointer 003010 [3]_ CACHE0.PUT CACHE0 pusher write pointer
003080 CACHE0.CTX CACHE0 puller context 003014 [3]_ CACHE0.STATUS CACHE0 status
003100 CACHE0.ADDR CACHE0 entry - address 003040 CACHE0.PULL_CTRL CACHE0 puller control
003104 CACHE0.DATA CACHE0 entry - data 003050 [1]_ CACHE0.PULL_STATE CACHE0 puller state
003200 CACHE1.PUSH_ACCESS CACHE1 pusher enable 003070 CACHE0.GET CACHE0 puller read pointer
003210 [1]_ CACHE1.CHID CACHE1 channel ID 003080 CACHE0.CTX CACHE0 puller context
003220 [1]_ CACHE1.STATUS CACHE1 status 003100 CACHE0.ADDR CACHE0 entry - address
003230 [1]_ CACHE1.PUT CACHE1 pusher write pointer 003104 CACHE0.DATA CACHE0 entry - data
003204 [3]_ CACHE1.CHID CACHE1 channel ID 003200 CACHE1.PUSH_ACCESS CACHE1 pusher enable
003210 [3]_ CACHE1.PUT CACHE1 pusher write pointer 003210 [1]_ CACHE1.CHID CACHE1 channel ID
003214 [3]_ CACHE1.STATUS CACHE1 status 003220 [1]_ CACHE1.STATUS CACHE1 status
003218 [3]_ CACHE1.DMA_STATE CACHE1 DMA pusher state 003230 [1]_ CACHE1.PUT CACHE1 pusher write pointer
003220 [3]_ CACHE1.DMA_CTRL CACHE1 DMA pusher control and status 003204 [3]_ CACHE1.CHID CACHE1 channel ID
003224 [3]_ CACHE1.DMA_COUNT CACHE1 DMA pusher data buffer counter 003210 [3]_ CACHE1.PUT CACHE1 pusher write pointer
003228 [3]_ CACHE1.DMA_GET CACHE1 DMA pusher data buffer pointer 003214 [3]_ CACHE1.STATUS CACHE1 status
00322c [3]_ CACHE1.DMA_TARGET CACHE1 DMA pusher data buffer target 003218 [3]_ CACHE1.DMA_STATE CACHE1 DMA pusher state
003230 [3]_ CACHE1.DMA_TLB_TAG CACHE1 DMA pusher data buffer TLB tag 003220 [3]_ CACHE1.DMA_CTRL CACHE1 DMA pusher control and status
003234 [3]_ CACHE1.DMA_TLB_PTE CACHE1 DMA pusher data buffer TLB entry 003224 [3]_ CACHE1.DMA_COUNT CACHE1 DMA pusher data buffer counter
003238 [3]_ CACHE1.DMA_PT_INST CACHE1 DMA pusher data buffer page table address 003228 [3]_ CACHE1.DMA_GET CACHE1 DMA pusher data buffer pointer
003240 CACHE1.PULL_CTRL CACHE1 puller control 00322c [3]_ CACHE1.DMA_TARGET CACHE1 DMA pusher data buffer target
003250 CACHE1.PULL_STATE CACHE1 puller state 003230 [3]_ CACHE1.DMA_TLB_TAG CACHE1 DMA pusher data buffer TLB tag
003270 CACHE1.GET CACHE1 puller read pointer 003234 [3]_ CACHE1.DMA_TLB_PTE CACHE1 DMA pusher data buffer TLB entry
003280+i*16 CACHE1.CTX[8] CACHE1 puller context 003238 [3]_ CACHE1.DMA_PT_INST CACHE1 DMA pusher data buffer page table address
003300+i*8 [2]_ CACHE1.ADDR[32] CACHE1 entries - address 003240 CACHE1.PULL_CTRL CACHE1 puller control
003304+i*8 [2]_ CACHE1.DATA[32] CACHE1 entries - data 003250 CACHE1.PULL_STATE CACHE1 puller state
003400+i*8 [4]_ CACHE1.ADDR[64] CACHE1 entries - address 003270 CACHE1.GET CACHE1 puller read pointer
003404+i*8 [4]_ CACHE1.DATA[64] CACHE1 entries - data 003280+i*16 CACHE1.CTX[8] CACHE1 puller context
=============== ===================== ============ 003300+i*8 [2]_ CACHE1.ADDR[32] CACHE1 entries - address
003304+i*8 [2]_ CACHE1.DATA[32] CACHE1 entries - data
003400+i*8 [4]_ CACHE1.ADDR[64] CACHE1 entries - address
003404+i*8 [4]_ CACHE1.DATA[64] CACHE1 entries - data
=============== ===================== ============




.. [0] available on NV01, NV03 and NV03T cards .. [0] available on NV01, NV03 and NV03T cards
Expand Down Expand Up @@ -264,3 +268,11 @@ RAMHT
===== =====


.. todo:: write me .. todo:: write me


USER submission area
====================

.. space:: 8 nv01-user 0x2000 PFIFO MMIO submission area

.. todo:: document me

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