Bus error on ARMv7 with Clang 8

[easyaspi314]

Clang erroneously produces ldrd instructions with t1ha with the unaligned code, and it causes bus errors.

ARM can do unaligned 64-bit reads with 2 ldr instructions, but ldrd requires an 8-byte aligned address.

More details hopefully to follow, but right now I am having difficulty with gdb ironically segfaulting.

[easyaspi314]

Got lldb to work. I attached a log.

lldblog.txt

Also, T1HA_UNALIGNED_ACCESS__SLOW worked.

[erthink]

In the attached log we can see that fetch64_le_unaligned() was called from line #213 inside t1ha2_atonce(). This is possible only when T1HA_SYS_UNALIGNED_ACCESS defined equal to T1HA_UNALIGNED_ACCESS__EFFICIENT (i.e. == 2).

In turn, T1HA_SYS_UNALIGNED_ACCESS can be defined externally as described in t1ha.h. Otherwise, by default (i.e. when T1HA_SYS_UNALIGNED_ACCESS not defined externally) the behavior will be determined by these lines.

So, for ARM-case the above may occur only when __ARM_FEATURE_UNALIGNED macro will be defined, and I don't see any error in the t1ha source code.

I can advise:

• refine and/or adjust compiler options to select the correct target platform (If the target hardware does NOT support unaligned access, then the __ARM_FEATURE_UNALIGNED macro should NOT be defined).
• use another (older) clang version or submit a bug-report.
• or just define T1HA_SYS_UNALIGNED_ACCESS == 0 in your makefile or any other convenient way.

[asheplyakov]

So, for ARM-case the above may occur only when __ARM_FEATURE_UNALIGNED

I think you misunderstand what __ARM_FEATURE_UNALIGNED means.
On armv7 unaligned access is possible only in some instructions for word- or halfword transfer, see https://www.keil.com/support/man/docs/armasm/armasm_dom1359731171041.htm

And nothing guarantees that such access is efficient.