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gpio.rs
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gpio.rs
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//! GPIO and pin configuration
use core::marker::PhantomData;
#[cfg(feature = "alloc")]
extern crate alloc;
#[cfg(feature = "alloc")]
use alloc::boxed::Box;
#[cfg(not(feature = "riscv-ulp-hal"))]
use esp_idf_sys::*;
#[cfg(feature = "riscv-ulp-hal")]
use crate::riscv_ulp_hal::sys::*;
use crate::adc::Adc;
use crate::peripheral::{Peripheral, PeripheralRef};
pub use chip::*;
/// A trait implemented by every pin instance
pub trait Pin: Peripheral<P = Self> + Sized + Send + 'static {
fn pin(&self) -> i32;
}
/// A marker trait designating a pin which is capable of
/// operating as an input pin
pub trait InputPin: Pin + Into<AnyInputPin> {
fn downgrade_input(self) -> AnyInputPin {
self.into()
}
}
/// A marker trait designating a pin which is capable of
/// operating as an output pin
pub trait OutputPin: Pin + Into<AnyOutputPin> {
fn downgrade_output(self) -> AnyOutputPin {
self.into()
}
}
/// A marker trait designating a pin which is capable of
/// operating as an input and output pin
pub trait IOPin: InputPin + OutputPin + Into<AnyIOPin> {
fn downgrade(self) -> AnyIOPin {
self.into()
}
}
/// A marker trait designating a pin which is capable of
/// operating as an RTC pin
pub trait RTCPin: Pin {
fn rtc_pin(&self) -> i32;
}
pub(crate) mod sealed {
pub trait ADCPin {
// NOTE: Will likely disappear in subsequent versions,
// once ADC support pops up in e-hal1. Hence sealed
const CHANNEL: super::adc_channel_t;
}
}
/// A marker trait designating a pin which is capable of
/// operating as an ADC pin
pub trait ADCPin: sealed::ADCPin + Pin {
type Adc: Adc;
fn adc_channel(&self) -> adc_channel_t {
Self::CHANNEL
}
}
/// A marker trait designating a pin which is capable of
/// operating as a DAC pin
#[cfg(all(not(esp32c3), not(esp32s3)))]
pub trait DACPin: Pin {
fn dac_channel(&self) -> dac_channel_t;
}
/// A marker trait designating a pin which is capable of
/// operating as a touch pin
#[cfg(not(esp32c3))]
pub trait TouchPin: Pin {
fn touch_channel(&self) -> touch_pad_t;
}
/// Generic Gpio input-output pin
pub struct AnyIOPin {
pin: i32,
_p: PhantomData<*const ()>,
}
impl AnyIOPin {
/// # Safety
///
/// Care should be taken not to instantiate this Pin, if it is
/// already instantiated and used elsewhere, or if it is not set
/// already in the mode of operation which is being instantiated
pub unsafe fn new(pin: i32) -> Self {
Self {
pin,
_p: PhantomData,
}
}
}
crate::impl_peripheral_trait!(AnyIOPin);
impl Pin for AnyIOPin {
fn pin(&self) -> i32 {
self.pin
}
}
impl InputPin for AnyIOPin {}
impl OutputPin for AnyIOPin {}
impl IOPin for AnyIOPin {}
/// Generic Gpio input pin
pub struct AnyInputPin {
pin: i32,
_p: PhantomData<*const ()>,
}
impl AnyInputPin {
/// # Safety
///
/// Care should be taken not to instantiate this Pin, if it is
/// already instantiated and used elsewhere, or if it is not set
/// already in the mode of operation which is being instantiated
pub unsafe fn new(pin: i32) -> Self {
Self {
pin,
_p: PhantomData,
}
}
}
crate::impl_peripheral_trait!(AnyInputPin);
impl Pin for AnyInputPin {
fn pin(&self) -> i32 {
self.pin
}
}
impl InputPin for AnyInputPin {}
impl From<AnyIOPin> for AnyInputPin {
fn from(pin: AnyIOPin) -> Self {
unsafe { Self::new(pin.pin()) }
}
}
/// Generic Gpio output pin
pub struct AnyOutputPin {
pin: i32,
_p: PhantomData<*const ()>,
}
impl AnyOutputPin {
/// # Safety
///
/// Care should be taken not to instantiate this Pin, if it is
/// already instantiated and used elsewhere, or if it is not set
/// already in the mode of operation which is being instantiated
pub unsafe fn new(pin: i32) -> Self {
Self {
pin,
_p: PhantomData,
}
}
}
crate::impl_peripheral_trait!(AnyOutputPin);
impl Pin for AnyOutputPin {
fn pin(&self) -> i32 {
self.pin
}
}
impl OutputPin for AnyOutputPin {}
impl From<AnyIOPin> for AnyOutputPin {
fn from(pin: AnyIOPin) -> Self {
unsafe { Self::new(pin.pin()) }
}
}
/// Interrupt types
#[cfg(all(not(feature = "riscv-ulp-hal"), feature = "alloc"))]
#[derive(Debug, Eq, PartialEq, Copy, Clone)]
pub enum InterruptType {
PosEdge,
NegEdge,
AnyEdge,
LowLevel,
HighLevel,
}
#[cfg(all(not(feature = "riscv-ulp-hal"), feature = "alloc"))]
impl From<InterruptType> for gpio_int_type_t {
fn from(interrupt_type: InterruptType) -> gpio_int_type_t {
match interrupt_type {
InterruptType::PosEdge => gpio_int_type_t_GPIO_INTR_POSEDGE,
InterruptType::NegEdge => gpio_int_type_t_GPIO_INTR_NEGEDGE,
InterruptType::AnyEdge => gpio_int_type_t_GPIO_INTR_ANYEDGE,
InterruptType::LowLevel => gpio_int_type_t_GPIO_INTR_LOW_LEVEL,
InterruptType::HighLevel => gpio_int_type_t_GPIO_INTR_HIGH_LEVEL,
}
}
}
/// Drive strength (values are approximates)
#[cfg(not(feature = "riscv-ulp-hal"))]
#[derive(Debug, Eq, PartialEq, Copy, Clone)]
pub enum DriveStrength {
I5mA = 0,
I10mA = 1,
I20mA = 2,
I40mA = 3,
}
#[cfg(not(feature = "riscv-ulp-hal"))]
impl From<DriveStrength> for gpio_drive_cap_t {
fn from(strength: DriveStrength) -> gpio_drive_cap_t {
match strength {
DriveStrength::I5mA => gpio_drive_cap_t_GPIO_DRIVE_CAP_0,
DriveStrength::I10mA => gpio_drive_cap_t_GPIO_DRIVE_CAP_1,
DriveStrength::I20mA => gpio_drive_cap_t_GPIO_DRIVE_CAP_2,
DriveStrength::I40mA => gpio_drive_cap_t_GPIO_DRIVE_CAP_3,
}
}
}
#[cfg(not(feature = "riscv-ulp-hal"))]
impl From<gpio_drive_cap_t> for DriveStrength {
#[allow(non_upper_case_globals)]
fn from(cap: gpio_drive_cap_t) -> DriveStrength {
match cap {
gpio_drive_cap_t_GPIO_DRIVE_CAP_0 => DriveStrength::I5mA,
gpio_drive_cap_t_GPIO_DRIVE_CAP_1 => DriveStrength::I10mA,
gpio_drive_cap_t_GPIO_DRIVE_CAP_2 => DriveStrength::I20mA,
gpio_drive_cap_t_GPIO_DRIVE_CAP_3 => DriveStrength::I40mA,
other => panic!("Unknown GPIO pin drive capability: {}", other),
}
}
}
// Pull setting for an input.
#[derive(Debug, Eq, PartialEq, Copy, Clone)]
pub enum Pull {
Floating,
Up,
Down,
UpDown,
}
impl From<Pull> for gpio_pull_mode_t {
fn from(pull: Pull) -> gpio_pull_mode_t {
match pull {
Pull::Floating => gpio_pull_mode_t_GPIO_FLOATING,
Pull::Up => gpio_pull_mode_t_GPIO_PULLUP_ONLY,
Pull::Down => gpio_pull_mode_t_GPIO_PULLDOWN_ONLY,
Pull::UpDown => gpio_pull_mode_t_GPIO_PULLUP_PULLDOWN,
}
}
}
/// Digital input or output level.
#[derive(Debug, Eq, PartialEq, Copy, Clone)]
pub enum Level {
Low,
High,
}
impl From<bool> for Level {
fn from(val: bool) -> Self {
match val {
true => Self::High,
false => Self::Low,
}
}
}
impl From<Level> for bool {
fn from(val: Level) -> bool {
match val {
Level::Low => false,
Level::High => true,
}
}
}
impl core::ops::Not for Level {
type Output = Level;
fn not(self) -> Self::Output {
match self {
Level::Low => Level::High,
Level::High => Level::Low,
}
}
}
pub trait InputMode {
const RTC: bool;
}
pub trait OutputMode {
const RTC: bool;
}
pub struct Disabled;
pub struct Input;
pub struct Output;
pub struct InputOutput;
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
pub struct RtcDisabled;
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
pub struct RtcInput;
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
pub struct RtcOutput;
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
pub struct RtcInputOutput;
impl InputMode for Input {
const RTC: bool = false;
}
impl InputMode for InputOutput {
const RTC: bool = false;
}
impl OutputMode for Output {
const RTC: bool = false;
}
impl OutputMode for InputOutput {
const RTC: bool = false;
}
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
impl InputMode for RtcInput {
const RTC: bool = true;
}
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
impl InputMode for RtcInputOutput {
const RTC: bool = true;
}
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
impl OutputMode for RtcOutput {
const RTC: bool = true;
}
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
impl OutputMode for RtcInputOutput {
const RTC: bool = true;
}
/// A driver for a GPIO pin.
///
/// The driver can set the pin as a disconnected/disabled one, input, or output pin, or both or analog.
/// On some chips (i.e. esp32 and esp32s*), the driver can also set the pin in RTC IO mode.
/// Depending on the current operating mode, different sets of functions are available.
///
/// The mode-setting depends on the capabilities of the pin as well, i.e. input-only pins cannot be set
/// into output or input-output mode.
pub struct PinDriver<'d, T: Pin, MODE> {
pin: PeripheralRef<'d, T>,
_mode: PhantomData<MODE>,
}
impl<'d, T: Pin> PinDriver<'d, T, Disabled> {
/// Creates the driver for a pin in disabled state.
#[inline]
pub fn disabled(pin: impl Peripheral<P = T> + 'd) -> Result<Self, EspError> {
crate::into_ref!(pin);
Self {
pin,
_mode: PhantomData,
}
.into_disabled()
}
}
impl<'d, T: InputPin> PinDriver<'d, T, Input> {
/// Creates the driver for a pin in input state.
#[inline]
pub fn input(pin: impl Peripheral<P = T> + 'd) -> Result<Self, EspError> {
crate::into_ref!(pin);
Self {
pin,
_mode: PhantomData,
}
.into_input()
}
}
impl<'d, T: InputPin + OutputPin> PinDriver<'d, T, InputOutput> {
/// Creates the driver for a pin in input-output state.
#[inline]
pub fn input_output(pin: impl Peripheral<P = T> + 'd) -> Result<Self, EspError> {
crate::into_ref!(pin);
Self {
pin,
_mode: PhantomData,
}
.into_input_output()
}
}
impl<'d, T: InputPin + OutputPin> PinDriver<'d, T, InputOutput> {
/// Creates the driver for a pin in input-output open-drain state.
#[inline]
pub fn input_output_od(pin: impl Peripheral<P = T> + 'd) -> Result<Self, EspError> {
crate::into_ref!(pin);
Self {
pin,
_mode: PhantomData,
}
.into_input_output_od()
}
}
impl<'d, T: OutputPin> PinDriver<'d, T, Output> {
/// Creates the driver for a pin in output state.
#[inline]
pub fn output(pin: impl Peripheral<P = T> + 'd) -> Result<Self, EspError> {
crate::into_ref!(pin);
Self {
pin,
_mode: PhantomData,
}
.into_output()
}
}
impl<'d, T: OutputPin> PinDriver<'d, T, Output> {
/// Creates the driver for a pin in output open-drain state.
#[inline]
pub fn output_od(pin: impl Peripheral<P = T> + 'd) -> Result<Self, EspError> {
crate::into_ref!(pin);
Self {
pin,
_mode: PhantomData,
}
.into_output_od()
}
}
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
impl<'d, T: Pin + RTCPin> PinDriver<'d, T, RtcDisabled> {
/// Creates the driver for a pin in disabled state.
#[inline]
pub fn rtc_disabled(pin: impl Peripheral<P = T> + 'd) -> Result<Self, EspError> {
crate::into_ref!(pin);
Self {
pin,
_mode: PhantomData,
}
.into_rtc_disabled()
}
}
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
impl<'d, T: InputPin + RTCPin> PinDriver<'d, T, RtcInput> {
/// Creates the driver for a pin in RTC input state.
#[inline]
pub fn rtc_input(pin: impl Peripheral<P = T> + 'd) -> Result<Self, EspError> {
crate::into_ref!(pin);
Self {
pin,
_mode: PhantomData,
}
.into_rtc_input()
}
}
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
impl<'d, T: InputPin + OutputPin + RTCPin> PinDriver<'d, T, RtcInputOutput> {
/// Creates the driver for a pin in RTC input-output state.
#[inline]
pub fn rtc_input_output(pin: impl Peripheral<P = T> + 'd) -> Result<Self, EspError> {
crate::into_ref!(pin);
Self {
pin,
_mode: PhantomData,
}
.into_rtc_input_output()
}
}
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
impl<'d, T: InputPin + OutputPin + RTCPin> PinDriver<'d, T, RtcInputOutput> {
/// Creates the driver for a pin in RTC input-output open-drain state.
#[inline]
pub fn rtc_input_output_od(pin: impl Peripheral<P = T> + 'd) -> Result<Self, EspError> {
crate::into_ref!(pin);
Self {
pin,
_mode: PhantomData,
}
.into_rtc_input_output_od()
}
}
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
impl<'d, T: OutputPin + RTCPin> PinDriver<'d, T, RtcOutput> {
/// Creates the driver for a pin in RTC output state.
#[inline]
pub fn rtc_output(pin: impl Peripheral<P = T> + 'd) -> Result<Self, EspError> {
crate::into_ref!(pin);
Self {
pin,
_mode: PhantomData,
}
.into_rtc_output()
}
}
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
impl<'d, T: OutputPin + RTCPin> PinDriver<'d, T, RtcOutput> {
/// Creates the driver for a pin in RTC output open-drain state.
#[inline]
pub fn rtc_output_od(pin: impl Peripheral<P = T> + 'd) -> Result<Self, EspError> {
crate::into_ref!(pin);
Self {
pin,
_mode: PhantomData,
}
.into_rtc_output_od()
}
}
impl<'d, T: Pin, MODE> PinDriver<'d, T, MODE> {
/// Returns the pin number.
pub fn pin(&self) -> i32 {
self.pin.pin()
}
/// Put the pin into disabled mode.
pub fn into_disabled(self) -> Result<PinDriver<'d, T, Disabled>, EspError> {
self.into_mode(gpio_mode_t_GPIO_MODE_DISABLE)
}
/// Put the pin into input mode.
#[inline]
pub fn into_input(self) -> Result<PinDriver<'d, T, Input>, EspError>
where
T: InputPin,
{
self.into_mode(gpio_mode_t_GPIO_MODE_INPUT)
}
/// Put the pin into input + output mode.
#[inline]
pub fn into_input_output(self) -> Result<PinDriver<'d, T, InputOutput>, EspError>
where
T: InputPin + OutputPin,
{
self.into_mode(gpio_mode_t_GPIO_MODE_INPUT_OUTPUT)
}
/// Put the pin into input + output Open Drain mode.
///
/// This is commonly used for "open drain" mode.
/// the hardware will drive the line low if you set it to low, and will leave it floating if you set
/// it to high, in which case you can read the input to figure out whether another device
/// is driving the line low.
#[inline]
pub fn into_input_output_od(self) -> Result<PinDriver<'d, T, InputOutput>, EspError>
where
T: InputPin + OutputPin,
{
self.into_mode(gpio_mode_t_GPIO_MODE_INPUT_OUTPUT_OD)
}
/// Put the pin into output mode.
#[inline]
pub fn into_output(self) -> Result<PinDriver<'d, T, Output>, EspError>
where
T: OutputPin,
{
self.into_mode(gpio_mode_t_GPIO_MODE_OUTPUT)
}
/// Put the pin into output Open Drain mode.
#[inline]
pub fn into_output_od(self) -> Result<PinDriver<'d, T, Output>, EspError>
where
T: OutputPin,
{
self.into_mode(gpio_mode_t_GPIO_MODE_OUTPUT_OD)
}
/// Put the pin into RTC disabled mode.
#[inline]
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
pub fn into_rtc_disabled(self) -> Result<PinDriver<'d, T, RtcDisabled>, EspError>
where
T: RTCPin,
{
self.into_rtc_mode(rtc_gpio_mode_t_RTC_GPIO_MODE_DISABLED)
}
/// Put the pin into RTC input mode.
#[inline]
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
pub fn into_rtc_input(self) -> Result<PinDriver<'d, T, RtcInput>, EspError>
where
T: InputPin + RTCPin,
{
self.into_rtc_mode(rtc_gpio_mode_t_RTC_GPIO_MODE_INPUT_ONLY)
}
/// Put the pin into RTC input + output mode.
///
/// This is commonly used for "open drain" mode.
/// the hardware will drive the line low if you set it to low, and will leave it floating if you set
/// it to high, in which case you can read the input to figure out whether another device
/// is driving the line low.
#[inline]
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
pub fn into_rtc_input_output(self) -> Result<PinDriver<'d, T, RtcInputOutput>, EspError>
where
T: InputPin + OutputPin + RTCPin,
{
self.into_rtc_mode(rtc_gpio_mode_t_RTC_GPIO_MODE_INPUT_OUTPUT)
}
/// Put the pin into RTC input + output Open Drain mode.
///
/// This is commonly used for "open drain" mode.
/// the hardware will drive the line low if you set it to low, and will leave it floating if you set
/// it to high, in which case you can read the input to figure out whether another device
/// is driving the line low.
#[inline]
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
pub fn into_rtc_input_output_od(self) -> Result<PinDriver<'d, T, RtcInputOutput>, EspError>
where
T: InputPin + OutputPin + RTCPin,
{
self.into_rtc_mode(rtc_gpio_mode_t_RTC_GPIO_MODE_INPUT_OUTPUT_OD)
}
/// Put the pin into RTC output mode.
#[inline]
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
pub fn into_rtc_output(self) -> Result<PinDriver<'d, T, RtcOutput>, EspError>
where
T: OutputPin + RTCPin,
{
self.into_rtc_mode(rtc_gpio_mode_t_RTC_GPIO_MODE_OUTPUT_ONLY)
}
/// Put the pin into RTC output Open Drain mode.
#[inline]
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
pub fn into_rtc_output_od(self) -> Result<PinDriver<'d, T, RtcOutput>, EspError>
where
T: OutputPin + RTCPin,
{
self.into_rtc_mode(rtc_gpio_mode_t_RTC_GPIO_MODE_OUTPUT_OD)
}
#[inline]
fn into_mode<M>(mut self, mode: gpio_mode_t) -> Result<PinDriver<'d, T, M>, EspError>
where
T: Pin,
{
let pin = unsafe { self.pin.clone_unchecked() };
drop(self);
if mode != gpio_mode_t_GPIO_MODE_DISABLE {
esp!(unsafe { gpio_set_direction(pin.pin(), mode) })?;
}
Ok(PinDriver {
pin,
_mode: PhantomData,
})
}
#[inline]
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
fn into_rtc_mode<M>(mut self, mode: rtc_gpio_mode_t) -> Result<PinDriver<'d, T, M>, EspError>
where
T: RTCPin,
{
let pin = unsafe { self.pin.clone_unchecked() };
drop(self);
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
{
esp!(unsafe { rtc_gpio_init(pin.pin()) })?;
esp!(unsafe { rtc_gpio_set_direction(pin.pin(), mode) })?;
}
Ok(PinDriver {
pin,
_mode: PhantomData,
})
}
#[inline]
#[cfg(not(feature = "riscv-ulp-hal"))]
pub fn get_drive_strength(&self) -> Result<DriveStrength, EspError>
where
MODE: OutputMode,
{
let mut cap: gpio_drive_cap_t = 0;
if MODE::RTC {
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
esp!(unsafe { rtc_gpio_get_drive_capability(self.pin.pin(), &mut cap) })?;
#[cfg(any(feature = "riscv-ulp-hal", esp32c3))]
unreachable!();
} else {
esp!(unsafe { gpio_get_drive_capability(self.pin.pin(), &mut cap) })?;
}
Ok(cap.into())
}
#[inline]
#[cfg(not(feature = "riscv-ulp-hal"))]
pub fn set_drive_strength(&mut self, strength: DriveStrength) -> Result<(), EspError>
where
MODE: OutputMode,
{
if MODE::RTC {
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
esp!(unsafe { rtc_gpio_set_drive_capability(self.pin.pin(), strength.into()) })?;
#[cfg(any(feature = "riscv-ulp-hal", esp32c3))]
unreachable!();
} else {
esp!(unsafe { gpio_set_drive_capability(self.pin.pin(), strength.into()) })?;
}
Ok(())
}
#[inline]
pub fn is_high(&self) -> bool
where
MODE: InputMode,
{
self.get_level().into()
}
#[inline]
pub fn is_low(&self) -> bool
where
MODE: InputMode,
{
!self.is_high()
}
#[inline]
pub fn get_level(&self) -> Level
where
MODE: InputMode,
{
let res;
if MODE::RTC {
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
{
res = if unsafe { rtc_gpio_get_level(self.pin.pin()) } != 0 {
Level::High
} else {
Level::Low
};
}
#[cfg(any(feature = "riscv-ulp-hal", esp32c3))]
unreachable!();
} else if unsafe { gpio_get_level(self.pin.pin()) } != 0 {
res = Level::High;
} else {
res = Level::Low;
}
res
}
#[inline]
pub fn is_set_high(&self) -> bool
where
MODE: OutputMode,
{
!self.is_set_low()
}
/// Is the output pin set as low?
#[inline]
pub fn is_set_low(&self) -> bool
where
MODE: OutputMode,
{
self.get_output_level() == Level::Low
}
/// What level output is set to
#[inline]
#[cfg(not(feature = "riscv-ulp-hal"))]
fn get_output_level(&self) -> Level
where
MODE: OutputMode,
{
// TODO: Implement for RTC mode
let pin = self.pin.pin() as u32;
#[cfg(esp32c3)]
let is_set_high = unsafe { (*(GPIO_OUT_REG as *const u32) >> pin) & 0x01 != 0 };
#[cfg(not(esp32c3))]
let is_set_high = if pin <= 31 {
// GPIO0 - GPIO31
unsafe { (*(GPIO_OUT_REG as *const u32) >> pin) & 0x01 != 0 }
} else {
// GPIO32+
unsafe { (*(GPIO_OUT1_REG as *const u32) >> (pin - 32)) & 0x01 != 0 }
};
if is_set_high {
Level::High
} else {
Level::Low
}
}
/// What level output is set to
#[inline]
#[cfg(feature = "riscv-ulp-hal")]
fn get_output_level(&self) -> Level
where
MODE: OutputMode,
{
if unsafe { gpio_get_output_level(self.pin.pin()) } != 0 {
Level::High
} else {
Level::Low
}
}
#[inline]
pub fn set_high(&mut self) -> Result<(), EspError>
where
MODE: OutputMode,
{
self.set_level(Level::High)
}
/// Set the output as low.
#[inline]
pub fn set_low(&mut self) -> Result<(), EspError>
where
MODE: OutputMode,
{
self.set_level(Level::Low)
}
#[inline]
pub fn set_level(&mut self, level: Level) -> Result<(), EspError>
where
MODE: OutputMode,
{
let on = match level {
Level::Low => 0,
Level::High => 1,
};
if MODE::RTC {
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
esp!(unsafe { rtc_gpio_set_level(self.pin.pin(), on) })?;
#[cfg(any(feature = "riscv-ulp-hal", esp32c3))]
unreachable!();
} else {
esp!(unsafe { gpio_set_level(self.pin.pin(), on) })?;
}
Ok(())
}
/// Toggle pin output
#[inline]
pub fn toggle(&mut self) -> Result<(), EspError>
where
MODE: OutputMode,
{
if self.is_set_low() {
self.set_high()
} else {
self.set_low()
}
}
pub fn set_pull(&mut self, pull: Pull) -> Result<(), EspError>
where
T: InputPin + OutputPin,
MODE: InputMode,
{
if MODE::RTC {
#[cfg(all(not(feature = "riscv-ulp-hal"), not(esp32c3)))]
unsafe {
match pull {
Pull::Down => {
esp!(rtc_gpio_pulldown_en(self.pin.pin()))?;
esp!(rtc_gpio_pullup_dis(self.pin.pin()))?;
}
Pull::Up => {
esp!(rtc_gpio_pulldown_dis(self.pin.pin()))?;
esp!(rtc_gpio_pullup_en(self.pin.pin()))?;
}
Pull::UpDown => {
esp!(rtc_gpio_pulldown_en(self.pin.pin()))?;
esp!(rtc_gpio_pullup_en(self.pin.pin()))?;
}
Pull::Floating => {
esp!(rtc_gpio_pulldown_dis(self.pin.pin()))?;
esp!(rtc_gpio_pullup_dis(self.pin.pin()))?;
}
}
}
#[cfg(any(feature = "riscv-ulp-hal", esp32c3))]
unreachable!();
} else {
esp!(unsafe { gpio_set_pull_mode(self.pin.pin(), pull.into()) })?;
}
Ok(())
}
/// # Safety
///
/// Care should be taken not to call STD, libc or FreeRTOS APIs (except for a few allowed ones)
/// in the callback passed to this function, as it is executed in an ISR context.
#[cfg(all(not(feature = "riscv-ulp-hal"), feature = "alloc"))]
pub unsafe fn subscribe(&mut self, callback: impl FnMut() + 'static) -> Result<(), EspError>
where
MODE: InputMode,
{
enable_isr_service()?;
self.unsubscribe()?;
let callback: Box<dyn FnMut() + 'static> = Box::new(callback);
chip::ISR_HANDLERS[self.pin.pin() as usize] = Some(Box::new(callback));
esp!(gpio_isr_handler_add(
self.pin.pin(),
Some(Self::handle_isr),
UnsafeCallback::from(
chip::ISR_HANDLERS[self.pin.pin() as usize]
.as_mut()
.unwrap(),
)
.as_ptr(),
))?;
self.enable_interrupt()?;
Ok(())
}
#[cfg(all(not(feature = "riscv-ulp-hal"), feature = "alloc"))]
pub fn unsubscribe(&mut self) -> Result<(), EspError>
where
MODE: InputMode,
{
unsafe {
unsubscribe_pin(self.pin.pin())?;
}