[Discussion] Remove the support of ADC2 digital controller on ESP32-S3 and ESP32-C3 (IDFGH-8691)

[ginkgm]

Due to the hardware limitation of ESP32-S3 and ESP32-C3 (See errata: S3 section 1.1, C3 section 1.1), we plan to remove the support for ADC2 in IDF drivers.

Affected:

• For S3, the digital controller (ADC-DMA) can't be used with ADC2, while you are still able to use ADC2 with RTC controller (one-shot).
• For C3, the ADC2 can't be used at all, because both one-shot and ADC-DMA are realized by digital controller.

For more details and questions, please contact sales@espressif.com.

We would like to adjust IDF drivers as follows:

• Print error and directly return from all the path that may make use of the digital controller with ADC2.
• If user insist on using it, turn on a Kconfig option. Then the driver will print warning and continue working. (As a back-compatible approach). In this case, user is on their own risk.

Suggestions are welcome.

[chipweinberger]

Errata in English: https://www.espressif.com/sites/default/files/documentation/esp32-s3_errata_en.pdf

1 SAR ADC
1.1 The Digital Controller (DMA) of SAR ADC2 cannot work
The Digital Controller of SAR ADC2 may receive a false sampling enable signal. In such case, the controller will
enter an inoperative state.
Users are suggested to use RTC controller to control SAR ADC2.
No fix scheduled.

[chipweinberger]

The suggested ESP-IDF changes sound good to me. Return error, with ability to KConfig old behavior.

[bbinet]

Could you please explain in more details what's wrong with ADC2 on esp32c3?
As we currently have boards for which GPIO05 is hardwired to measure external analog voltage, what is the actual risk if we continue to use ADC2 using CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3 option?
Until now, we do not experience any issue with ADC2 here, and we would prefer to avoid a hardware redesign of the board...

[Icarus113]

@bbinet The ADC oneshot mode is controlled by a digital controller and this digital controller has some deficiencies, a potential issue that we observed is that, on some chips you may get 0 raw result, even if you connect it to a certain level.

[bbinet]

Ok, so the only risk is to get some wrong values (raw value equals 0) from time to time?
So I could ignore values which equals 0, and I'll be fine, right?

[Icarus113]

Hi, @bbinet , the 0 result is just one of the potential issues, it appears on some chips. Generally speaking, the results from ADC2 aren't reliable.

So I could ignore values which equals 0, and I'll be fine, right?

I would say no. We can't guarantee other results are correct.

[bbinet]

Thank you @Icarus113 for this information.

[Icarus113]

Hi watchers, the code changes for this issue have been merged in to all related releases.

If there's no other comments, I'm gonna close this issue in 1 day.

[chegewara]

Hi,
i think it may be good to make this topic/issue pinned.

[moefear85]

so what this means is, if continuous sampling adc1 and adc2 simultaneously, then even if sampling starts fine... at any random moment, a spurious sampling enable may happen, that then causes the entire DMA controller to crash, hence making all read attempts after that fail?

If this is correct, then, if user code determines such a failed state has been entered, is it possible to simply reconfigure the adc and start over, or would it require a restart of the entire chip?

[Icarus113]

so what this means is, if continuous sampling adc1 and adc2 simultaneously, then even if sampling starts fine... at any random moment, a spurious sampling enable may happen, that then causes the entire DMA controller to crash, hence making all read attempts after that fail?

Actually I don't actually know if this will be one of the conditions. (I didn't meet such scenario yet).

if user code determines such a failed state has been entered, is it possible to simply reconfigure the adc and start over, or would it require a restart of the entire chip?

The problem is that, there's no flag or similar thing indicating issue happens. And you can't recover it by reconfigure adc or restart the whole chip. The issue is always there.

@moefear85

[moefear85]

strange... either way please leave the functionality available if possible, ie don't deprecate it. I find it very useful and the results I'm getting seem fine. Hopefully it might be fixed in a future revision of the chip.

[devitalii]

ok, so on C3 model A5 is the only one that is on ADC2, ADC1 is A0-A4.