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Generating a Rocket32s1 with smaller cache #208
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I believe you need to put cache parameters before
Yes, just look into generated device tree file - system.dts |
Thank you! That was it. I was able to generate small cores with other cache sizes. With the 'normal' WithNSmallCores (unmodified caches) I get from the UART:
(This is a benchmark from tacle-bench, which I compiled with riscv toolchain and added some measurements.) xsdb gives me:
But when I program my core with modified cache, I do get the output from the boot rom. But I cannot connect to the target, the Hart is not listed.
Do you have any ideas? |
I have now tried to boot my (bare-metal) program from the SD-card. Since I used the mk-sd-card script, it was easier to boot from a 64-bit bootloader/program, so I moved to the Rocket64b1 core. When I boot from the SD-card, my program always runs fine. But when using xsdb, I can only connect to the Hart #0 on a core with unmodified cache sizes. Again, when I modify the cache size (both ICache and DCache, e.g. 32K or 64K) then the Hart #0 (Running) won't show. Hope you have some pointers on how to investigate this. Using xsdb is a lot more friendly than the SD card :-) |
I cannot reproduce. I tried this config:
xsdb appears working fine. |
I use Vitis 2022.2. I must say I don't use Ubuntu, but Archlinux. I decided to try to build the bitstreams on another machine, and they seem to be running fine. A difference between the two machines was that on the one that wasn't building OK, I had a separate sbt and scala installed. I removed them, and now this machine also seems to build OK. I'm still not sure whether this was the solution. The cores that I have built today do run my benchmarks, but strangely I don't see the bootrom printing messages anymore. Is it safe to follow your most recent master branch? Or should I switch to one of your releases? Thanks for your help! |
Vitis 2022.2 should be OK.
Most likely it is issue with serial port setup on your host machine. |
Hi Eugene,
Great project! I have a question about generating a small rocket core with even smaller cache than the standard one.
I added the following to src/main/scala/rocket.scala:
and then I did
make CONFIG=rocket32s1_extrasmallcache BOARD=genesys2 bitstream
The thing is, I tried several benchmarks and compared it with the 'normal' Rocket32s1, and the results (number of cycles) remains the same. Which is suspicious to me. Do you know if my approach to generating a core with smaller cache is right? Is there any method or tool that I could use to verify the resulting cache size?
Thnx!
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