Joining the forces?

[XVilka]

Some time ago I opened a discussion about creating truly common middle-level HDL/representation, see the f4pga/ideas#19

It would be nice to hear your opinion, maybe even it's possible to join the forces.

[fabianschuiki]

I think it would be a great idea to join forces in this regard! Your list of points on what such an IR HDL would need pretty much matches up with what I have observed so far.

My ultimate goal is to capture SystemVerilog, Verilog, and VHDL in its entirety -- with an initial focus on synthesis/simulation. I also want to maintain compatibility with existing commercial tools, to avoid a "ideological" biforcation of the community into either an open-source and commercial lock-in. I would hope that we could eventually move a lot of the language frontend part into the open source domain, to allow for language innovation and have the tool vendors focus on their core business.

As a first step I think it would be great to tie moore/llhd into the SymbiFlow compliance suite and start exploring ways to support the flow with LLHD, e.g. by using moore as a frontend to feed designs.

What do you think?

[XVilka]

Yes, that was the idea.