Emit assert/assume as call to llhd.assert
intrinsic
#222
Labels
A-codegen
Area: Code generation.
C-enhancement
Category: Adding or improving on features.
E-easy
Call for Participation: Easy issue, good first issue.
L-vlog
Language: Verilog and SystemVerilog.
Immediate assertions are currently ignored. As a first step to some minimally-useful implementation, lower them to a call to
llhd.assert
. Possibly something along the lines of:The text was updated successfully, but these errors were encountered: