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problems about ports when build in hierachy #231

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Zhangyanting-1997 opened this issue Sep 8, 2021 · 1 comment
Open

problems about ports when build in hierachy #231

Zhangyanting-1997 opened this issue Sep 8, 2021 · 1 comment
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A-mir Area: Mid-level Intermediate Representation. C-bug Category: This is a bug. L-vlog Language: Verilog and SystemVerilog. P-high Priority: High.

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@Zhangyanting-1997
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When doing module instantiation, an error occurs when a port exists.
Netlist.zip
截屏2021-09-08 下午11 07 34
@fabianschuiki
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Hi @Zhangyanting-1997, thanks for reporting the issue. This is indeed a compiler bug and should be working.

@fabianschuiki fabianschuiki added A-mir Area: Mid-level Intermediate Representation. C-bug Category: This is a bug. L-vlog Language: Verilog and SystemVerilog. P-high Priority: High. labels Sep 9, 2021
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A-mir Area: Mid-level Intermediate Representation. C-bug Category: This is a bug. L-vlog Language: Verilog and SystemVerilog. P-high Priority: High.
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