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mstar-v7.dtsi
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mstar-v7.dtsi
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2020 thingy.jp.
* Author: Daniel Palmer <daniel@thingy.jp>
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mstar-msc313-mpll.h>
#include <dt-bindings/clock/mstar-msc313-gater.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
clocks = <&cpupll>;
clock-names = "cpuclk";
};
};
arch_timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2)
| IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2)
| IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2)
| IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2)
| IRQ_TYPE_LEVEL_LOW)>;
/*
* we shouldn't need this but the vendor
* u-boot is broken
*/
clock-frequency = <6000000>;
arm,cpu-registers-not-fw-configured;
};
pmu: pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
/* interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; */
interrupt-affinity = <&cpu0>;
};
clocks: clocks {
unknownclk: unknownclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <1>;
};
/*
* For the msc313e there is only a 24mhz clock input so everything else must come
* from this base clock unless there are some on-die oscillators that aren't mentioned
* anywhere.
*/
xtal: xtal {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
xtal12: xtal12 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&xtal>;
clock-div = <2>;
clock-mult = <1>;
};
rtc_xtal: rtc_xtal {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
status = "disabled";
};
rtc32k_div4: rtc32k_div4 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&rtc_xtal>;
clock-div = <4>;
clock-mult = <1>;
};
xtal12_div2: xtal12_div2 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&xtal12>;
clock-div = <2>;
clock-mult = <1>;
};
xtal12_div4: xtal12_div4 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&xtal12>;
clock-div = <4>;
clock-mult = <1>;
};
xtal12_div8: xtal12_div8 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&xtal12>;
clock-div = <8>;
clock-mult = <1>;
};
xtal12_div12: xtal12_div12 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&xtal12>;
clock-div = <12>;
clock-mult = <1>;
};
xtal12_div16: xtal12_div16 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&xtal12>;
clock-div = <16>;
clock-mult = <1>;
};
xtal12_div40: xtal12_div40 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&xtal12>;
clock-div = <40>;
clock-mult = <1>;
};
xtal12_div64: xtal12_div64 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&xtal12>;
clock-div = <64>;
clock-mult = <1>;
};
xtal12_div128: xtal12_div128 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&xtal12>;
clock-div = <128>;
clock-mult = <1>;
};
clk_mpll_86_div2: clk_mpll_86_div2 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&clkgen_pll MSTAR_MPLL_GATE_MPLL_86>;
clock-div = <2>;
clock-mult = <1>;
};
clk_mpll_86_div4: clk_mpll_86_div4 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&clkgen_pll MSTAR_MPLL_GATE_MPLL_86>;
clock-div = <4>;
clock-mult = <1>;
};
clk_mpll_86_div16: clk_mpll_86_div16 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&clkgen_pll MSTAR_MPLL_GATE_MPLL_86>;
clock-div = <16>;
clock-mult = <1>;
};
clk_mpll_123_div2: clk_mpll_123_div2 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&clkgen_pll MSTAR_MPLL_GATE_MPLL_123>;
clock-div = <2>;
clock-mult = <1>;
};
clk_mpll_144_div2: clk_mpll_144_div2 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&clkgen_pll MSTAR_MPLL_GATE_MPLL_144>;
clock-div = <2>;
clock-mult = <1>;
};
clk_mpll_144_div4: clk_mpll_144_div4 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&clkgen_pll MSTAR_MPLL_GATE_MPLL_144>;
clock-div = <4>;
clock-mult = <1>;
};
clk_utmi_160_div4: clk_utmi_160_div4 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&clkgen_pll MSTAR_MPLL_GATE_UTMI_160>;
clock-div = <4>;
clock-mult = <1>;
};
clk_utmi_160_div5: clk_utmi_160_div5 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&clkgen_pll MSTAR_MPLL_GATE_UTMI_160>;
clock-div = <5>;
clock-mult = <1>;
};
clk_utmi_160_div8: clk_utmi_160_div8 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&clkgen_pll MSTAR_MPLL_GATE_UTMI_160>;
clock-div = <8>;
clock-mult = <1>;
};
clk_utmi_192_div4: clk_utmi_192_div4 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&clkgen_pll MSTAR_MPLL_GATE_UTMI_192>;
clock-div = <4>;
clock-mult = <1>;
};
clk_mpll_216_div2: clk_mpll_216_div2 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&clkgen_pll MSTAR_MPLL_GATE_MPLL_216>;
clock-div = <2>;
clock-mult = <1>;
};
clk_mpll_216_div4: clk_mpll_216_div4 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&clkgen_pll MSTAR_MPLL_GATE_MPLL_216>;
clock-div = <4>;
clock-mult = <1>;
};
clk_mpll_216_div8: clk_mpll_216_div8 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&clkgen_pll MSTAR_MPLL_GATE_MPLL_216>;
clock-div = <8>;
clock-mult = <1>;
};
clk_mpll_288_div2: clk_mpll_288_div2 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&clkgen_pll MSTAR_MPLL_GATE_MPLL_288>;
clock-div = <2>;
clock-mult = <1>;
};
clk_mpll_288_div4: clk_mpll_288_div4 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&clkgen_pll MSTAR_MPLL_GATE_MPLL_288>;
clock-div = <4>;
clock-mult = <1>;
};
clk_mpll_288_div8: clk_mpll_288_div8 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&clkgen_pll MSTAR_MPLL_GATE_MPLL_288>;
clock-div = <8>;
clock-mult = <1>;
};
emac_phyclk: emac_phyclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
pad2isp_sr_pclk: pad2isp_sr_pclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <1>;
};
csi2_mac: csi2_mac {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
/*
* this is a dummy for now, there must be a switch for the
* cpu clk to move between the mpll and the xtal, the spi nor
* controller also uses this clock and it works before the
* mpll is enabled
*/
cpuclksrc: cpuclksrc {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&clkgen_pll MSTAR_MPLL_GATE_MPLL_432>;
clock-div = <1>;
clock-mult = <1>;
};
};
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x14000000 0x14000000 0x1000000>,
<0x16001000 0x16001000 0x00007000>,
<0x1f000000 0x1f000000 0x00400000>,
<0xa0000000 0xa0000000 0x20000>;
isp: isp@1f001000 {
compatible = "mstar,msc313-isp";
reg = <0x1f001000 0x400>,
<0x1f002c00 0x200>,
<0x1f002e00 0x200>,
<0x14000000 0x1000000>;
clock-names = "pm_spi", "cpuclk", "spi";
clocks = <&clkgen_mux_spi_mcu_pm 1>, <&cpuclksrc>, <&clkgen_mux_spi 0>;
interrupts-extended = <&intc_irq GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&bdma 0>, <&bdma 1>;
dma-names = "qspi", "qspi";
pinctrl-names = "default";
pinctrl-0 = <&pm_spi_pins>;
status = "disabled";
interconnects = <&miu 0>;
interconnect-names = "dma-mem";
};
/*
temp_sensor {
compatible = "iio-hwmon";
io-channels = <&sar 4>;
};
*/
efuse: efuse@0x1f004000 {
compatible = "mstar,msc313-efuse";
reg = <0x1f004000 0x8>;
};
ir: ir@1f007a00 {
// maybe
interrupts-extended = <&intc_fiq GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<&intc_fiq GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@16001000 {
compatible = "arm,cortex-a7-gic";
reg = <0x16001000 0x1000>,
<0x16002000 0x2000>,
<0x16004000 0x2000>,
<0x16006000 0x2000>;
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2)
| IRQ_TYPE_LEVEL_LOW)>;
};
riu: bus@1f000000 {
compatible = "simple-bus";
//compatible = "mstar,riubrdg";
reg = <0x1f000000 0x00400000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1f000000 0x00400000>;
clocks = <&clkgen_mux_mcu_riubrdg 1>;
interrupts-extended = <&intc_irq GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
pmsleep: syscon@1c00 {
/* msc313e notes
*
* 1f001c24 -- bit 11 disables pm uart rx
* -- bit 15 is set when going into deep sleep
*
*
* 0x1f001cec -- return address after resume
* 0x1f001cf0
* 0x1f001cf4 -- clk for timers?
* 0x1f001cc0 -- ??
* 0x1f001cc8 -- set to 9fe8 before deep sleep
* 0x1f001ccc -- set to 9fe8 before deep sleep
* 0x1f001cdc -- set to 0xa5 before deep sleep
*/
compatible = "mstar,msc313-pmsleep", "syscon";
reg = <0x1c00 0x100>;
};
reboot {
compatible = "syscon-reboot";
regmap = <&pmsleep>;
offset = <0xb8>;
mask = <0x79>;
};
pinctrl_pm: pinctrl@1c00 {
mstar,pmsleep = <&pmsleep>;
pm_uart_pins: pm_uart {
function = "pm_uart";
groups = "pm_uart";
};
pm_spi_pins: pm_spi {
function = "pm_spi";
groups = "pm_spi";
};
pm_irin_pins: pm_irin {
function = "pm_irin";
groups = "pm_irin";
};
};
pmintc: interrupt-controller@1c10 {
compatible = "mstar,msc313-pm-intc";
interrupt-parent = <&intc_irq>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
mstar,pmsleep = <&pmsleep>;
};
wakeintc: interrupt-controller@1c20 {
compatible = "mstar,msc313-pm-wakeup-intc";
interrupt-parent = <&intc_irq>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
mstar,pmsleep = <&pmsleep>;
};
clkgen_mux_spi_mcu_pm: clkgen_mux@1c80 {
compatible = "mstar,msc313e-clkgen-mux";
reg = <0x1c80 0x4>;
#clock-cells = <1>;
clock-output-names = "mcu_pm", "spi_pm";
shifts = <0>, <8>;
mstar,deglitches = <7>, <14>;
mux-shifts = <2>, <10>;
mux-widths = <4>, <4>;
mux-ranges = <0 2>, <2 17>;
clocks = /* mcu_pm */
<&clkgen_pll MSTAR_MPLL_GATE_MPLL_216>,
/* deglitch */
<&xtal12>,
/* spi_pm */
<&rtc_xtal>,
<&clk_mpll_216_div8>,
<&clk_mpll_144_div4>,
<&clk_mpll_86_div2>,
<&clk_mpll_216_div4>,
<&clk_mpll_144_div2>,
<&clkgen_pll MSTAR_MPLL_GATE_MPLL_86>,
<&clk_mpll_216_div2>,
<&xtal12_div8>,
<&xtal12_div12>,
<&rtc32k_div4>,
<&xtal12_div16>,
<&xtal12_div2>,
<&xtal12_div4>,
<&xtal12>,
<&xtal>,
/* deglitch */
<&xtal12>;
assigned-clocks = <&clkgen_mux_spi_mcu_pm 1>;
assigned-clock-parents = <&clk_mpll_216_div4>;
assigned-clock-rates = <0>;
};
clkgen_mux_ir: clkgen_mux@1c84 {
compatible = "mstar,msc313e-clkgen-mux";
reg = <0x1c84 0x4>;
#clock-cells = <1>;
clock-output-names = "ir";
shifts = <5>;
mux-shifts = <7>;
mux-widths = <3>;
clocks = <&xtal12>,
<&rtc_xtal>,
<&xtal12_div8>,
<&xtal12_div12>,
<&rtc32k_div4>,
<&xtal12_div16>,
<&xtal12_div2>,
<&xtal12_div4>;
};
clkgen_mux_rtc_sar: clkgen_mux@1c88 {
compatible = "mstar,msc313e-clkgen-mux";
reg = <0x1c88 0x4>;
#clock-cells = <1>;
clock-output-names = "rtc", "sar", "pm_sleep";
shifts = <0>, <5>, <10>;
mux-shifts = <2>, <7>, <12>;
mux-widths = <2>, <3>, <3>;
mux-ranges = <0 2>, <0 8>, <0 8>;
clocks = <&xtal12>,
<&rtc_xtal>,
<&xtal12_div8>,
<&xtal12_div12>,
<&rtc32k_div4>,
<&xtal12_div16>,
<&xtal12_div2>,
<&xtal12_div4>;
};
gpio_pm: gpio_pm@1e00 {
reg = <0x1e00 0x200>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&pmintc>;
status = "disabled";
};
mcu: mcu@2000 {
compatible = "mstar,msc313-pm51";
reg = <0x2000 0x200>;
mstar,pmsleep = <&pmsleep>;
clocks = <&clkgen_mux_spi_mcu_pm 0>;
dma-names = "bdma0", "bdma1";
dmas = <&bdma 0>, <&bdma 1>;
interconnects = <&miu 0>;
interconnect-names = "dma-mem";
interrupts-extended = <&intc_fiq GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
};
rtc: rtc@2400 {
compatible = "mstar,msc313-rtc";
reg = <0x2400 0x40>;
clocks = <&clkgen_mux_rtc_sar 0>;
interrupts-extended = <&intc_irq GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<&wakeintc 4 IRQ_TYPE_LEVEL_HIGH>;
wakeup-source;
};
sar: sar@2800 {
reg = <0x2800 0x200>;
interrupts-extended = <&intc_irq GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<&wakeintc 1 IRQ_TYPE_LEVEL_HIGH>,
<&wakeintc 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc_fiq GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<&intc_fiq GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<&intc_fiq GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<&intc_fiq GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sar",
"wakeup",
"wakeup_gpio",
"sar_gpio0",
"sar_gpio1",
"sar_gpio2",
"sar_gpio3";
clock-names = "sar_clk";
clocks = <&clkgen_mux_rtc_sar 1>;
#gpio-cells = <2>;
mstar,pmsleep = <&pmsleep>;
wakeup-source;
status = "disabled";
sar0_gpio0_pins: sar0_gpio0 {
function = "sar0";
groups = "sar_gpio0";
};
sar1_gpio1_pins: sar1_gpio1 {
function = "sar1";
groups = "sar_gpio1";
};
sar2_gpio2_pins: sar2_gpio2 {
function = "sar2";
groups = "sar_gpio2";
};
sar3_gpio3_pins: sar3_gpio3 {
function = "sar3";
groups = "sar_gpio3";
};
};
wdt: wdt@6000 {
compatible = "mstar,msc313e-wdt";
reg = <0x6000 0x1f>;
clocks = <&xtal12>;
interrupts-extended = <&intc_fiq GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
};
timer0: timer@6040 {
compatible = "mstar,msc313e-timer";
reg = <0x6040 0x40>;
clocks = <&xtal12>;
interrupts-extended = <&intc_fiq GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
//mstar,schedclk;
};
timer1: timer@6080 {
compatible = "mstar,msc313e-timer";
reg = <0x6080 0x40>;
clocks = <&xtal12>;
interrupts-extended = <&intc_fiq GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
//mstar,tick;
};
timer2: timer@60c0 {
compatible = "mstar,msc313e-timer";
reg = <0x60c0 0x40>;
clocks = <&xtal12>;
interrupts-extended = <&intc_fiq GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
};
intc_fiq: interrupt-controller@201310 {
compatible = "mstar,mst-intc";
reg = <0x201310 0x40>;
#interrupt-cells = <3>;
interrupt-controller;
interrupt-parent = <&gic>;
mstar,irqs-map-range = <96 127>;
};
intc_irq: interrupt-controller@201350 {
compatible = "mstar,mst-intc";
reg = <0x201350 0x40>;
#interrupt-cells = <3>;
interrupt-controller;
interrupt-parent = <&gic>;
mstar,irqs-map-range = <32 95>;
mstar,intc-no-eoi;
};
pinctrl: pinctrl@203c00 {
reg = <0x203c00 0x200>;
emac_pins: eth {
function = "eth";
groups = "eth";
};
fuart_pins: fuart {
function = "fuart";
groups = "fuart";
};
fuart_mode1_pins: fuart_mode1 {
function = "fuart";
groups = "fuart_mode1";
};
fuart_mode2_pins: fuart_mode2 {
function = "fuart";
groups = "fuart_mode2";
};
fuart_mode3_pins: fuart_mode3 {
function = "fuart";
groups = "fuart_mode3";
};
fuart_mode4_pins: fuart_mode4 {
function = "fuart";
groups = "fuart_mode4";
};
fuart_mode5_pins: fuart_mode5 {
function = "fuart";
groups = "fuart_mode5";
};
fuart_mode6_pins: fuart_mode6 {
function = "fuart";
groups = "fuart_mode6";
};
fuart_mode7_pins: fuart_mode7 {
function = "fuart";
groups = "fuart_mode7";
};
fuart_rx_tx_rts_pins: fuart_rx_tx_rts {
function = "fuart";
groups = "fuart_rx_tx_rts";
};
uart1_mode1_pins: uart1_mode1 {
function = "uart1";
groups = "uart_mode1";
};
uart1_pins: uart1 {
function = "uart1";
groups = "fuart_cts_rts";
};
uart1_cts_pins: uart1_cts {
function = "uart1";
groups = "fuart_cts";
};
i2c0_pins: i2c0 {
function = "i2c0";
groups = "i2c0";
};
i2c1_pins: i2c1 {
function = "i2c1";
groups = "i2c1";
};
i2c1_mode1_pins: i2c1_mode1 {
function = "i2c1";
groups = "i2c1_mode1";
};
i2c1_mode3_pins: i2c1_mode3 {
function = "i2c1";
groups = "i2c1_mode3";
};
i2c1_mode4_pins: i2c1_mode4 {
function = "i2c1";
groups = "i2c1_mode4";
};
i2c1_mode5_pins: i2c1_mode5 {
function = "i2c1";
groups = "i2c1_mode5";
};
spi0_spi0_pins: spi0_spi0 {
function = "spi0";
groups = "spi0";
};
spi0_fuart_pins: spi0_fuart {
function = "spi0";
groups = "fuart";
};
spi1_sd_d0_d1_d2_d3_pins: spi1_sd_d0_d1_d2_d3 {
function = "spi1";
groups = "sd_d0_d1_d2_d3";
};
sdio_pins: sdio {
function = "sdio";
groups = "sd";
bias-pull-up;
};
usb_pins: usb {
function = "usb";
groups = "usb";
};
usb1_pins: usb1 {
function = "usb1";
groups = "usb1";
};
};
bdma: bdma@200400 {
compatible = "mstar,msc313-bdma";
reg = <0x200400 0x80>;
interrupt-parent = <&intc_irq>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkgen_mux_bdma 0>;
dma-channels = <2>;
status = "okay";
#dma-cells = <1>;
};
mailbox: mailbox@200800 {
reg = <0x200800 0x200>;
/*
* 0x0 - boot rom writes 0xbabe here right near the start.
* 0x4 - something to do with "SRAM and MCM gates".
* 0x8 - boot rom writes values into here during startup.
* seems to be for debugging?
* 0x20 - 24 - vendor kernel writes the log buf addr here. Debugging?
*/
};
miu: miu@202000 {
compatible = "mstar,msc313-miu";
reg = <0x202000 0x200>,
<0x202400 0x200>,
<0x202200 0x200>;
interrupt-parent = <&intc_irq>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "miu", "ddr";
clocks = <&clkgen_mux_miu 0>, <&clkgen_mux_ddrsyn 0>;
/*mstar,rd-timing = <0xB>;*/
mstar,trcd = <0x6>;
mstar,trp = <0x6>;
#clock-cells = <0>;
clock-output-names = "ddrpll";
dma-ranges = <0x00000000 0x20000000 0x4000000>;
#interconnect-cells = <1>;
};
l3bridge: l3bridge@204400 {
compatible = "mstar,l3bridge", "syscon";
reg = <0x204400 0x200>;
status = "disabled";
};
mpll: mpll@206000 {
compatible = "mstar,msc313-mpll";
#clock-cells = <1>;
reg = <0x206000 0x200>;
clocks = <&xtal>;
clock-output-names = "1f206000.mpll", "1f206000.mpll_div_2",
"1f206000.mpll_div_3", "1f206000.mpll_div_4",
"1f206000.mpll_div_5", "1f206000.mpll_div_6",
"1f206000.mpll_div_7", "1f206000.mpll_div_10";
};
miupll: miupll@206200 {
compatible = "mstar,miupll";
reg = <0x206200 0x200>;
#clock-cells = <0>;
clocks = <&xtal>;
};
cpupll: cpupll@206400 {
compatible = "mstar,msc313-cpupll";
reg = <0x206400 0x200>;
#clock-cells = <0>;
clocks = <&cpuclksrc>;
};
lpll: lpll@206700 {
compatible = "mstar,msc313-lpll";
reg = <0x206700 0x100>;
#clock-cells = <0>;
clocks = <&clkgen_pll MSTAR_MPLL_GATE_MPLL_432>;
};
clkgen_pll: pll-gater@2071c0 {
compatible = "mstar,msc313-pll-gater";
reg = <0x2071c0 0x10>;
#clock-cells = <1>;
clock-output-names = "upll_384_gate", "upll_320_gate", "utmi_160_gate", "utmi_192_gate",
"utmi_240_gate", "utmi_480_gate", "mpll_432_gate", "mpll_345_gate",
"mpll_288_gate", "mpll_216_gate", "mpll_172_gate", "mpll_144_gate",
"mpll_123_gate", "mpll_124_gate", "mpll_86_gate", "pll_rv1_gate";
clocks = <&upll 0>,
<&upll 1>,
<&unknownclk>,
<&unknownclk>,
<&unknownclk>,
<&unknownclk>,
<&mpll MSTAR_MSC313_MPLL_DIV2>,
<&unknownclk>,
<&mpll MSTAR_MSC313_MPLL_DIV3>,
<&mpll MSTAR_MSC313_MPLL_DIV4>,
<&mpll MSTAR_MSC313_MPLL_DIV5>,
<&mpll MSTAR_MSC313_MPLL_DIV6>,
<&mpll MSTAR_MSC313_MPLL_DIV7>,
<&unknownclk>,
<&mpll MSTAR_MSC313_MPLL_DIV10>,
<&unknownclk>;
};
gpio: gpio@207800 {
#gpio-cells = <2>;
reg = <0x207800 0x200>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
interrupt-parent = <&intc_fiq>;
status = "disabled";
};
clkgen_mux_miu: clkgen_mux@20705c {
compatible = "mstar,msc313e-clkgen-mux";
reg = <0x20705c 0x4>;
#clock-cells = <1>;
clock-output-names = "miu";
output-flags = <MSTAR_CLKGEN_OUTPUTFLAG_CRITICAL>;
shifts = <0>;
mux-shifts = <2>;
mux-widths = <2>;
mstar,deglitches = <4>;
clocks = <&clkgen_pll MSTAR_MPLL_GATE_MPLL_216>,
<&miupll>,
<&unknownclk>,
<&unknownclk>,
<&xtal12>;
};
clkgen_mux_miu_rec: clkgen_mux@207060 {
compatible = "mstar,msc313e-clkgen-mux";
reg = <0x207060 0x4>;
#clock-cells = <1>;
clock-output-names = "miu_rec";
shifts = <0>;
mux-shifts = <2>;
mux-widths = <2>;
clocks = <&xtal12_div8>,
<&xtal12_div16>,
<&xtal12_div64>,
<&xtal12_div128>;
};
clkgen_mux_ddrsyn: clkgen_mux@207064 {
compatible = "mstar,msc313e-clkgen-mux";
reg = <0x207064 0x4>;
#clock-cells = <1>;
clock-output-names = "ddrsyn";
output-flags = <MSTAR_CLKGEN_OUTPUTFLAG_CRITICAL>;
shifts = <0>;
mux-shifts = <2>;
mux-widths = <2>;
clocks = <&clkgen_pll MSTAR_MPLL_GATE_MPLL_432>,
<&clkgen_pll MSTAR_MPLL_GATE_MPLL_216>,
<&xtal12>;
};
clkgen_mux_mspi: clkgen_mux@2070cc {
compatible = "mstar,msc313e-clkgen-mux";
reg = <0x2070cc 0x4>;
#clock-cells = <1>;
clock-output-names = "mspi0", "mspi1";
shifts = <0>, <8>;
mux-shifts = <2>, <10>;
mux-widths = <2>, <2>;
clocks = <&clk_mpll_216_div2>,
<&clk_mpll_216_div4>,
<&xtal12>;
};
clkgen_mux_miic: clkgen_mux@2070dc {
compatible = "mstar,msc313e-clkgen-mux";
reg = <0x2070dc 0x4>;
#clock-cells = <1>;
clock-output-names = "miic0", "miic1";
shifts = <0>, <8>;
mux-shifts = <2>, <10>;
mux-widths = <2>, <2>;
clocks = <&clk_mpll_288_div4>,
<&clk_mpll_216_div4>,
<&xtal12>;
};
clkgen_mux_emac: clkgen_mux@207108 {
compatible = "mstar,msc313e-clkgen-mux";
reg = <0x207108 0x4>;
#clock-cells = <1>;
clock-output-names = "emac_ahb";
shifts = <0>;
mux-shifts = <2>;
mux-widths = <2>;
output-flags = <0x800>; /* this marks the clock as critical, gating this clock stops access to the registers */
clocks = <&clk_mpll_288_div2>,
<&clkgen_pll MSTAR_MPLL_GATE_MPLL_123>,
<&clkgen_pll MSTAR_MPLL_GATE_MPLL_86>;
/* from lan_atop ? */
};
clkgen_mux_bdma: clkgen_mux@207180 {
compatible = "mstar,msc313e-clkgen-mux";
reg = <0x207180 0x4>;
#clock-cells = <1>;
clock-output-names = "bdma";
shifts = <0>;
mux-shifts = <2>;
mux-widths = <2>;
mstar,deglitches = <4>;
clocks = <&clkgen_mux_miu 0>,
/* deglitch */
<&xtal12>;
/*assigned-clocks = <&clkgen_mux_bdma 0>;
assigned-clock-parents = <&clkgen_mux_miu 0>;
assigned-clock-rates = <0>;*/
};
fuart: uart@220400 {
compatible = "mstar,msc313-uart";
reg = <0x220400 0x100>;
interrupt-parent = <&intc_irq>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <3>;
clocks = <&clkgen_mux_fuart 0>;
pinctrl-names = "default";
pinctrl-0 = <&fuart_pins>;
status = "disabled";
};
urdma: urdma@220600 {
compatible = "mstar,msc313-urdma";
reg = <0x220600 0x100>;
interrupts-extended = <&intc_irq GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&miu 0>;
};
pm_uart: uart@221000 {
compatible = "mstar,msc313-uart";
reg = <0x221000 0x100>;
reg-shift = <3>;
interrupts-extended = <&intc_irq GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkgen_mux_uart 0>;
pinctrl-names = "default";
pinctrl-0 = <&pm_uart_pins>;
status = "disabled";
};
uart1: uart@221200 {
compatible = "mstar,msc313-uart";