/
csr.yaml
3196 lines (3196 loc) · 119 KB
/
csr.yaml
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---
addr:
rw:
mask: 3072
lsb: 10
values:
- values: 0, 1, 2
key: RW
desc: Read Write
- values: 3
key: RO
desc: Read Only
priv:
mask: 768
lsb: 8
values:
- values: 0
key: U
desc: User
- values: 1
key: S
desc: Supervisor
- values: 2
key: H
desc: Hypervisor
- values: 3
key: M
desc: Machine
use:
mask: 240
lsb: 4
values:
- values: 11XX
desc: Custom
- values: 1010
desc: Debug
- values: 1011
desc: Debug
regs:
bsatp:
priv: HRW
number: 640
bscause:
number: 578
priv: HRW
bsepc:
number: 577
priv: HRW
bsie:
number: 516
priv: HRW
bsip:
number: 580
priv: HRW
bsscratch:
number: 576
priv: HRW
bsstatus:
number: 512
priv: HRW
bstval:
number: 579
priv: HRW
bstvec:
number: 517
priv: HRW
cycle:
number: 3072
desc: Cycle counter for RDCYCLE instruction.
priv: URO
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
mmio: false
sections:
machine:
- "/riscv-isa-manual/latest/machine.html#machine-counter-inhibit-csr-mcountinhibit"
- "/riscv-isa-manual/latest/machine.html#machine-scratch-register-mscratch"
supervisor:
- "/riscv-isa-manual/latest/supervisor.html#counter-enable-register-scounteren"
- "/riscv-isa-manual/latest/supervisor.html#supervisor-scratch-register-sscratch"
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
- "/riscv-isa-manual/latest/hypervisor.html#trap-entry"
counters:
- "/riscv-isa-manual/latest/counters.html#zihpm-standard-extension-for-hardware-performance-counters"
debug:
- "/riscv-debug-spec/latest/core_registers.html#debug-pc-dpc-at-0x7b1"
cycleh:
number: 3200
desc: Upper 32 bits of cycle, RV32I only.
priv: URO
url: "/riscv-isa-manual/latest/machine.html#machine-counter-inhibit-csr-mcountinhibit"
mmio: false
sections:
machine:
- "/riscv-isa-manual/latest/machine.html#machine-counter-inhibit-csr-mcountinhibit"
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#trap-entry"
dcsr:
number: 1968
desc: Debug control and status register.
priv: DRW
url: "/riscv-debug-spec/latest/core_registers.html#debug-control-and-status-dcsr-at-0x7b0"
sections:
debug:
- "/riscv-debug-spec/latest/core_registers.html#debug-control-and-status-dcsr-at-0x7b0"
- "/riscv-debug-spec/latest/debug_module.html#dmi"
- "/riscv-debug-spec/latest/core_debug.html#load-reservedstore-conditional-instructions"
- "/riscv-debug-spec/latest/core_debug.html#xlen"
- "/riscv-debug-spec/latest/debugger_implementation.html#accessing-registers"
dpc:
number: 1969
desc: Debug PC.
priv: DRW
url: "/riscv-debug-spec/latest/core_debug.html#load-reservedstore-conditional-instructions"
mmio: false
sections:
debug:
- "/riscv-debug-spec/latest/core_debug.html#load-reservedstore-conditional-instructions"
- "/riscv-debug-spec/latest/core_registers.html#debug-pc-dpc-at-0x7b1"
- "/riscv-debug-spec/latest/Sdext.html#load-reservedstore-conditional-instructions"
- "/riscv-debug-spec/latest/core_registers.html#debug-control-and-status-dcsr-at-0x7b0"
- "/riscv-debug-spec/latest/debug_module.html#dmi"
- "/riscv-debug-spec/latest/debug_module.html#overview-of-states"
- "/riscv-debug-spec/latest/core_debug.html#xlen"
- "/riscv-debug-spec/latest/core_registers.html#debug-scratch-register-0-dscratch0-at-0x7b2"
- "/riscv-debug-spec/latest/abstract_commands.html#quick-access"
dscratch:
number: 1970
url: "/riscv-debug-spec/latest/dm_registers.html#hart-array-window-select-hawindowsel-at-0x14"
sections:
debug:
- "/riscv-debug-spec/latest/dm_registers.html#hart-array-window-select-hawindowsel-at-0x14"
dscratch0:
number: 1970
desc: Debug scratch register 0.
priv: DRW
url: "/riscv-debug-spec/latest/dm_registers.html#hart-array-window-select-hawindowsel-at-0x14"
mmio: false
sections:
debug:
- "/riscv-debug-spec/latest/dm_registers.html#hart-array-window-select-hawindowsel-at-0x14"
- "/riscv-debug-spec/latest/core_registers.html#debug-scratch-register-0-dscratch0-at-0x7b2"
- "/riscv-debug-spec/latest/core_registers.html#debug-control-and-status-dcsr-at-0x7b0"
dscratch1:
number: 1971
desc: Debug scratch register 1.
priv: DRW
url: "/riscv-debug-spec/latest/dm_registers.html#hart-array-window-select-hawindowsel-at-0x14"
mmio: false
sections:
debug:
- "/riscv-debug-spec/latest/dm_registers.html#hart-array-window-select-hawindowsel-at-0x14"
- "/riscv-debug-spec/latest/core_registers.html#debug-scratch-register-1-dscratch1-at-0x7b3"
- "/riscv-debug-spec/latest/core_registers.html#debug-control-and-status-dcsr-at-0x7b0"
fcsr:
number: 3
desc: Floating-Point Control and Status
priv: URW
url: "/riscv-isa-manual/latest/machine.html#machine-trap-vector-base-address-register-mtvec"
mmio: false
sections:
v-spec:
- "/riscv-v-spec/draft/v-spec.html#_vector_fixed_point_fields_in_code_fcsr_code"
machine:
- "/riscv-isa-manual/latest/machine.html#machine-trap-vector-base-address-register-mtvec"
f:
- "/riscv-isa-manual/latest/f.html#floating-point-control-and-status-register"
- "/riscv-isa-manual/latest/f.html#nan-generation-and-propagation"
dep-table:
- "/riscv-isa-manual/latest/dep-table.html#sec:source-dest-regs"
fflags:
number: 1
desc: Floating-Point Accrued Exceptions.
priv: URW
url: "/riscv-isa-manual/latest/memory.html#sec:memory:ppopipeline"
mmio: false
sections:
machine:
- "/riscv-isa-manual/latest/machine.html#machine-trap-vector-base-address-register-mtvec"
f:
- "/riscv-isa-manual/latest/f.html#nan-generation-and-propagation"
dep-table:
- "/riscv-isa-manual/latest/dep-table.html#sec:source-dest-regs"
memory:
- "/riscv-isa-manual/latest/memory.html#sec:memory:ppopipeline"
v-spec:
- "/riscv-v-spec/draft/v-spec.html#_vector_single_width_floating_point_addsubtract_instructions"
debug:
- "/riscv-debug-spec/latest/abstract_commands.html#quick-access"
frm:
number: 2
desc: Floating-Point Dynamic Rounding Mode.
priv: URW
url: "/riscv-isa-manual/latest/dep-table.html#sec:source-dest-regs"
mmio: false
sections:
machine:
- "/riscv-isa-manual/latest/machine.html#machine-trap-vector-base-address-register-mtvec"
f:
- "/riscv-isa-manual/latest/f.html#nan-generation-and-propagation"
dep-table:
- "/riscv-isa-manual/latest/dep-table.html#sec:source-dest-regs"
v-spec:
- "/riscv-v-spec/draft/v-spec.html#sec-widening"
- "/riscv-v-spec/draft/v-spec.html#_widening_floating_pointinteger_type_convert_instructions"
hcontext:
number: 1704
desc: Hypervisor-mode context register.
priv: HRW
url: "/riscv-debug-spec/latest/hwbp_registers.html#hypervisor-context-hcontext-at-0x6a8"
sections:
debug:
- "/riscv-debug-spec/latest/hwbp_registers.html#hypervisor-context-hcontext-at-0x6a8"
- "/riscv-debug-spec/latest/hwbp_registers.html#trigger-select-tselect-at-0x7a0"
hcounteren:
number: 1542
desc: Hypervisor counter enable.
priv: HRW
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-counter-enable-register-hcounteren"
mmio: false
sections:
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-counter-enable-register-hcounteren"
- "/riscv-isa-manual/latest/hypervisor.html#trap-entry"
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-status-register-hstatus"
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hedeleg:
number: 1538
desc: Hypervisor exception delegation register.
priv: HRW
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-trap-delegation-registers-hedeleg-and-hideleg"
mmio: false
sections:
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-trap-delegation-registers-hedeleg-and-hideleg"
- "/riscv-isa-manual/latest/hypervisor.html#sec:tinst-vals"
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-status-register-hstatus"
- "/riscv-isa-manual/latest/hypervisor.html#sec:hinterruptregs"
debug:
- "/riscv-debug-spec/latest/Sdtrig.html#memory-access-triggers"
henvcfg:
number: 1546
desc: Hypervisor environment configuration register.
priv: HRW
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-counter-enable-register-hcounteren"
sections:
machine:
- "/riscv-isa-manual/latest/machine.html#sec:mseccfg"
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-counter-enable-register-hcounteren"
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-status-register-hstatus"
henvcfgh:
number: 1562
desc: Additional hypervisor env. conf. register, RV32 only.
priv: HRW
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-counter-enable-register-hcounteren"
sections:
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-counter-enable-register-hcounteren"
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-status-register-hstatus"
hgatp:
number: 1664
desc: Hypervisor guest address translation and protection.
priv: HRW
url: "/riscv-isa-manual/latest/hypervisor.html#sec:hgatp"
mmio: false
sections:
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#sec:hgatp"
- "/riscv-isa-manual/latest/hypervisor.html#traps"
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-status-register-hstatus"
- "/riscv-isa-manual/latest/hypervisor.html#virtual-supervisor-status-register-vsstatus"
- "/riscv-isa-manual/latest/hypervisor.html#machine-level-csrs"
- "/riscv-isa-manual/latest/hypervisor.html#machine-interrupt-delegation-register-mideleg"
- "/riscv-isa-manual/latest/hypervisor.html#sec:guest-addr-translation"
- "/riscv-isa-manual/latest/hypervisor.html#guest-page-faults"
machine:
- "/riscv-isa-manual/latest/machine.html#sec:mseccfg"
- "/riscv-isa-manual/latest/machine.html#sec:nmi"
supervisor:
- "/riscv-isa-manual/latest/supervisor.html#svinval"
hgeie:
number: 1543
desc: Hypervisor guest external interrupt-enable register.
priv: HRW
url: "/riscv-isa-manual/latest/hypervisor.html#sec:hgeinterruptregs"
mmio: false
sections:
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#sec:hgeinterruptregs"
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-environment-configuration-registers-henvcfg-and-henvcfgh"
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-status-register-hstatus"
hgeip:
number: 3602
desc: Hypervisor guest external interrupt pending.
priv: HRO
url: "/riscv-isa-manual/latest/hypervisor.html#sec:hgeinterruptregs"
mmio: false
sections:
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#sec:hgeinterruptregs"
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-environment-configuration-registers-henvcfg-and-henvcfgh"
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-status-register-hstatus"
hideleg:
number: 1539
desc: Hypervisor interrupt delegation register.
priv: HRW
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-trap-delegation-registers-hedeleg-and-hideleg"
mmio: false
sections:
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-trap-delegation-registers-hedeleg-and-hideleg"
- "/riscv-isa-manual/latest/hypervisor.html#sec:tinst-vals"
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-status-register-hstatus"
- "/riscv-isa-manual/latest/hypervisor.html#sec:hinterruptregs"
- "/riscv-isa-manual/latest/hypervisor.html#sec:hgeinterruptregs"
- "/riscv-isa-manual/latest/hypervisor.html#virtual-supervisor-trap-vector-base-address-register-vstvec"
- "/riscv-isa-manual/latest/hypervisor.html#machine-interrupt-registers-mip-and-mie"
hie:
number: 1540
desc: Hypervisor interrupt-enable register.
priv: HRW
url: "/riscv-isa-manual/latest/hypervisor.html#sec:hinterruptregs"
mmio: false
sections:
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#sec:hinterruptregs"
- "/riscv-isa-manual/latest/hypervisor.html#machine-second-trap-value-register-mtval2"
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-status-register-hstatus"
- "/riscv-isa-manual/latest/hypervisor.html#sec:hgeinterruptregs"
- "/riscv-isa-manual/latest/hypervisor.html#virtual-supervisor-trap-vector-base-address-register-vstvec"
- "/riscv-isa-manual/latest/hypervisor.html#machine-interrupt-registers-mip-and-mie"
hip:
number: 1604
desc: Hypervisor interrupt pending.
priv: HRW
url: "/riscv-isa-manual/latest/hypervisor.html#sec:hinterruptregs"
mmio: false
sections:
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#sec:hinterruptregs"
- "/riscv-isa-manual/latest/hypervisor.html#machine-second-trap-value-register-mtval2"
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-status-register-hstatus"
- "/riscv-isa-manual/latest/hypervisor.html#sec:hgeinterruptregs"
- "/riscv-isa-manual/latest/hypervisor.html#virtual-supervisor-trap-vector-base-address-register-vstvec"
- "/riscv-isa-manual/latest/hypervisor.html#machine-interrupt-registers-mip-and-mie"
hpmcounter10:
number: 3082
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter10h:
number: 3210
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter11:
number: 3083
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter11h:
number: 3211
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter12:
number: 3084
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter12h:
number: 3212
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter13:
number: 3085
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter13h:
number: 3213
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter14:
number: 3086
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter14h:
number: 3214
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter15:
number: 3087
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter15h:
number: 3215
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter16:
number: 3088
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter16h:
number: 3216
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter17:
number: 3089
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter17h:
number: 3217
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter18:
number: 3090
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter18h:
number: 3218
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter19:
number: 3091
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter19h:
number: 3219
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter20:
number: 3092
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter20h:
number: 3220
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter21:
number: 3093
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter21h:
number: 3221
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter22:
number: 3094
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter22h:
number: 3222
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter23:
number: 3095
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter23h:
number: 3223
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter24:
number: 3096
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter24h:
number: 3224
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter25:
number: 3097
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter25h:
number: 3225
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter26:
number: 3098
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter26h:
number: 3226
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter27:
number: 3099
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter27h:
number: 3227
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter28:
number: 3100
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter28h:
number: 3228
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter29:
number: 3101
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter29h:
number: 3229
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter3:
number: 3075
desc: Performance-monitoring counter.
priv: URO
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
mmio: false
sections:
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter30:
number: 3102
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter30h:
number: 3230
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter31:
number: 3103
desc: Performance-monitoring counter.
priv: URO
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
mmio: false
sections:
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter31h:
number: 3231
desc: Upper 32 bits of hpmcounter31, RV32I only.
priv: URO
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
mmio: false
sections:
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter3h:
number: 3203
desc: Upper 32 bits of hpmcounter3, RV32I only.
priv: URO
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
mmio: false
sections:
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter4:
number: 3076
desc: Performance-monitoring counter.
priv: URO
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
mmio: false
sections:
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter4h:
number: 3204
desc: Upper 32 bits of hpmcounter4, RV32I only.
priv: URO
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
mmio: false
sections:
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter5:
number: 3077
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter5h:
number: 3205
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter6:
number: 3078
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter6h:
number: 3206
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter7:
number: 3079
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter7h:
number: 3207
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter8:
number: 3080
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter8h:
number: 3208
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter9:
number: 3081
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hpmcounter9h:
number: 3209
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
hstatus:
number: 1536
desc: Hypervisor status register.
priv: HRW
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-status-register-hstatus"
mmio: false
sections:
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-status-register-hstatus"
- "/riscv-isa-manual/latest/hypervisor.html#sec:tinst-vals"
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-trap-delegation-registers-hedeleg-and-hideleg"
- "/riscv-isa-manual/latest/hypervisor.html#sec:hgeinterruptregs"
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-environment-configuration-registers-henvcfg-and-henvcfgh"
- "/riscv-isa-manual/latest/hypervisor.html#virtual-supervisor-status-register-vsstatus"
- "/riscv-isa-manual/latest/hypervisor.html#virtual-supervisor-interrupt-registers-vsip-and-vsie"
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-instructions"
- "/riscv-isa-manual/latest/hypervisor.html#sec:hfence.vma"
- "/riscv-isa-manual/latest/hypervisor.html#machine-level-csrs"
- "/riscv-isa-manual/latest/hypervisor.html#machine-interrupt-delegation-register-mideleg"
- "/riscv-isa-manual/latest/hypervisor.html#trap-entry"
htimedelta:
number: 1541
desc: Delta for VS/VU-mode timer.
priv: HRW
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
mmio: false
sections:
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
- "/riscv-isa-manual/latest/hypervisor.html#trap-entry"
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-status-register-hstatus"
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-trap-value-register-htval"
htimedeltah:
number: 1557
desc: Upper 32 bits of htimedelta, RV32I only.
priv: HRW
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
mmio: false
sections:
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
- "/riscv-isa-manual/latest/hypervisor.html#trap-entry"
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-status-register-hstatus"
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-trap-value-register-htval"
htinst:
number: 1610
desc: Hypervisor trap instruction (transformed).
priv: HRW
url: "/riscv-isa-manual/latest/hypervisor.html#sec:tinst-vals"
mmio: false
sections:
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#sec:tinst-vals"
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-trap-instruction-register-htinst"
- "/riscv-isa-manual/latest/hypervisor.html#trap-return"
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-status-register-hstatus"
- "/riscv-isa-manual/latest/hypervisor.html#sec:hgatp"
- "/riscv-isa-manual/latest/hypervisor.html#memory-management-fences"
htval:
number: 1603
desc: Hypervisor bad guest physical address.
priv: HRW
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-trap-value-register-htval"
mmio: false
sections:
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-trap-value-register-htval"
- "/riscv-isa-manual/latest/hypervisor.html#trap-return"
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-status-register-hstatus"
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-trap-instruction-register-htinst"
- "/riscv-isa-manual/latest/hypervisor.html#machine-level-csrs"
- "/riscv-isa-manual/latest/hypervisor.html#memory-management-fences"
- "/riscv-isa-manual/latest/hypervisor.html#sec:tinst-vals"
hvip:
number: 1605
desc: Hypervisor virtual interrupt pending.
priv: HRW
url: "/riscv-isa-manual/latest/hypervisor.html#sec:hinterruptregs"
sections:
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#sec:hinterruptregs"
- "/riscv-isa-manual/latest/hypervisor.html#sec:hgeinterruptregs"
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-status-register-hstatus"
instret:
number: 3074
desc: Instructions-retired counter for RDINSTRET instruction.
priv: URO
url: "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
mmio: false
sections:
machine:
- "/riscv-isa-manual/latest/machine.html#machine-counter-inhibit-csr-mcountinhibit"
- "/riscv-isa-manual/latest/machine.html#machine-scratch-register-mscratch"
supervisor:
- "/riscv-isa-manual/latest/supervisor.html#counter-enable-register-scounteren"
- "/riscv-isa-manual/latest/supervisor.html#supervisor-scratch-register-sscratch"
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
counters:
- "/riscv-isa-manual/latest/counters.html#zihpm-standard-extension-for-hardware-performance-counters"
debug:
- "/riscv-debug-spec/latest/core_registers.html#debug-pc-dpc-at-0x7b1"
instreth:
number: 3202
desc: Upper 32 bits of instret, RV32I only.
priv: URO
url: "/riscv-isa-manual/latest/machine.html#machine-counter-inhibit-csr-mcountinhibit"
mmio: false
sections:
machine:
- "/riscv-isa-manual/latest/machine.html#machine-counter-inhibit-csr-mcountinhibit"
marchid:
url: "/riscv-isa-manual/latest/machine.html#machine-architecture-id-register-marchid"
width: mxlen
mmio: false
desc: Machine Architecture ID
number: 3858
priv: MRO
sections:
machine:
- "/riscv-isa-manual/latest/machine.html#machine-architecture-id-register-marchid"
- "/riscv-isa-manual/latest/machine.html#machine-implementation-id-register-mimpid"
mbase:
number: 896
desc: Base register.
priv: MRW
mbound:
number: 897
desc: Bound register.
priv: MRW
mcause:
url: "/riscv-isa-manual/latest/machine.html#machine-cause-register-mcause"
mmio: false
width: mxlen
desc: Machine Exception Cause
fields:
interrupt:
desc: Interrupt (1) or Trap (0)
bits:
- mxlen-1
enums:
INTERRUPT: 1
TRAP: 0
interrupt_code:
desc: Code identifying the last interrupt
condition:
mask: 1<<(mxlen-1)
value: 1<<(mxlen-1)
bits:
- mxlen-2
- 0
enums:
msi: 3
mti: 7
mei: 11
ssi: 1
sti: 5
sei: 9
usi: 0
uti: 4
uei: 8
platform_defined16: 16
platform_defined17: 17
platform_defined18: 18
platform_defined19: 19
platform_defined20: 20
platform_defined21: 21
platform_defined22: 22
platform_defined23: 23
platform_defined24: 24
platform_defined25: 25
platform_defined26: 26
platform_defined27: 27
platform_defined28: 28
platform_defined29: 29
platform_defined30: 30
platform_defined31: 31
exception_code:
desc: Code identifying the last exception.
condition:
mask: 1<<(mxlen-1)
value: 0
bits:
- mxlen-2
- 0
enums:
INSTRUCTION_ADDRESS_MISALIGNED: 0
INSTRUCTION_ACCESS_FAULT: 1
ILLEGAL_INSTRUCTION: 2
BREAKPOINT: 3
LOAD_ADDRESS_MISALIGNED: 4
LOAD_ACCESS_FAULT: 5
STORE_AMO_ADDRESS_MISALIGNED: 6
STORE_AMO_ACCESS_FAULT: 7
ENVIRONMENT_CALL_FROM_U_MODE: 8
ENVIRONMENT_CALL_FROM_S_MODE: 9
RESERVED10: 10
ENVIRONMENT_CALL_FROM_M_MODE: 11
INSTRUCTION_PAGE_FAULT: 12
LOAD_PAGE_FAULT: 13
RESERVED14: 14
STORE_AMO_PAGE_FAULT: 15
RESERVED16: 16
RESERVED17: 17
RESERVED18: 18
RESERVED19: 19
RESERVED20: 20
RESERVED21: 21
RESERVED22: 22
RESERVED23: 23
CUSTOM24: 24
CUSTOM25: 25
CUSTOM26: 26
CUSTOM27: 27
CUSTOM28: 28
CUSTOM29: 29
CUSTOM30: 30
CUSTOM31: 31
RESERVED32: 32
RESERVED33: 33
RESERVED34: 34
RESERVED35: 35
RESERVED36: 36
RESERVED37: 37
RESERVED38: 38
RESERVED39: 39
RESERVED40: 40
RESERVED41: 41
RESERVED42: 42
RESERVED43: 43
RESERVED44: 44
RESERVED45: 45
RESERVED46: 46
RESERVED47: 47
RESERVED48: 48
RESERVED49: 49
RESERVED50: 50
RESERVED51: 51
RESERVED52: 52
RESERVED53: 53
RESERVED54: 54
RESERVED55: 55
RESERVED56: 56
RESERVED57: 57
RESERVED58: 58
RESERVED59: 59
RESERVED60: 60
RESERVED61: 61
RESERVED62: 62
RESERVED63: 63
number: 834
priv: MRW
sections:
machine:
- "/riscv-isa-manual/latest/machine.html#sec:mcause"
- "/riscv-isa-manual/latest/machine.html#machine-interrupt-registers-mip-and-mie"
- "/riscv-isa-manual/latest/machine.html#hardware-performance-monitor"
- "/riscv-isa-manual/latest/machine.html#machine-trap-value-register-mtval"
- "/riscv-isa-manual/latest/machine.html#sec:nmi"
- "/riscv-isa-manual/latest/machine.html#sec:pma"
plic:
- "/riscv-isa-manual/latest/plic.html#global-interrupt-sources"
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#trap-entry"
- "/riscv-isa-manual/latest/hypervisor.html#sec:tinst-vals"
n:
- "/riscv-isa-manual/latest/n.html#n-extension-instructions"
debug:
- "/riscv-debug-spec/latest/Sdtrig.html#memory-access-triggers"
- "/riscv-debug-spec/latest/hwbp_registers.html#external-trigger-tmexttrigger-at-0x7a1"
- "/riscv-debug-spec/latest/hwbp_registers.html#trigger-extra-rv32-textra32-at-0x7a3"
mconfigptr:
number: 3861
desc: Pointer to configuration data structure.
priv: MRO
url: "/riscv-isa-manual/latest/machine.html#machine-configuration-pointer-register-mconfigptr"
sections:
machine:
- "/riscv-isa-manual/latest/machine.html#machine-configuration-pointer-register-mconfigptr"
- "/riscv-isa-manual/latest/machine.html#machine-environment-configuration-registers-menvcfg-and-menvcfgh"
mcontext:
number: 1960
desc: Machine-mode context register.
priv: MRW
url: "/riscv-debug-spec/latest/hwbp_registers.html#machine-context-mcontext-at-0x7a8"
sections:
debug:
- "/riscv-debug-spec/latest/hwbp_registers.html#machine-context-mcontext-at-0x7a8"
- "/riscv-debug-spec/latest/hwbp_registers.html#trigger-select-tselect-at-0x7a0"
- "/riscv-debug-spec/latest/hwbp_registers.html#trigger-extra-rv64-textra64-at-0x7a3"
- "/riscv-debug-spec/latest/hwbp_registers.html#supervisor-context-scontext-at-0x7aa"
mcounteren:
url: "/riscv-isa-manual/latest/machine.html#sec:mcounteren"
mmio: false
width: 32
desc: Counter Enable
number: 774
priv: MRW
sections:
machine:
- "/riscv-isa-manual/latest/machine.html#sec:mcounteren"
- "/riscv-isa-manual/latest/machine.html#machine-counter-inhibit-csr-mcountinhibit"
supervisor:
- "/riscv-isa-manual/latest/supervisor.html#supervisor-scratch-register-sscratch"
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#trap-entry"
- "/riscv-isa-manual/latest/hypervisor.html#hypervisor-time-delta-registers-htimedelta-htimedeltah"
fields:
cy:
desc: Prevent access to 'cycle' counter from lower priveledge level
bits:
- 0
tm:
desc: Prevent access to 'time' counter from lower priveledge level
bits:
- 1
ir:
desc: Prevent access to 'instret' counter from lower priveledge level
bits:
- 2
hpm:
desc: Prevent access to 'hpm3' to 'hpm31' counter from lower priveledge level
bits:
- 31
- 3
mcountinhibit:
url: "/riscv-isa-manual/latest/machine.html#machine-counter-inhibit-csr-mcountinhibit"
mmio: false
width: 32
desc: Machine Counter Inhibit
number: 800
priv: MRW
sections:
machine:
- "/riscv-isa-manual/latest/machine.html#machine-counter-inhibit-csr-mcountinhibit"
- "/riscv-isa-manual/latest/machine.html#machine-scratch-register-mscratch"
fields:
cy:
desc: Disable incrementing the 'cycle' counter
bits:
- 0
ir:
desc: Disable incrementing the 'instret' counter
bits:
- 2
hpm:
desc: Disable incrementing the 'hpm3' to 'hpm31' counter.
bits:
- 31
- 3
mcycle:
url: "/riscv-isa-manual/latest/machine.html#hardware-performance-monitor"
mmio: false
width: 64
desc: Clock Cycles Executed Counter
per_hart: true
number: 2816
priv: MRW
sections:
machine:
- "/riscv-isa-manual/latest/machine.html#machine-scratch-register-mscratch"
- "/riscv-isa-manual/latest/machine.html#sec:mcounteren"
- "/riscv-isa-manual/latest/machine.html#machine-counter-inhibit-csr-mcountinhibit"
mcycleh:
number: 2944
desc: Upper 32 bits of mcycle, RV32I only.
width: 32
arch: rv32
priv: MRW
url: "/riscv-isa-manual/latest/machine.html#machine-counter-inhibit-csr-mcountinhibit"
mmio: false
sections:
machine:
- "/riscv-isa-manual/latest/machine.html#machine-counter-inhibit-csr-mcountinhibit"
- "/riscv-isa-manual/latest/machine.html#sec:mcounteren"
mdbase:
number: 900
desc: Data base register.
priv: MRW
mdbound:
number: 901
desc: Data bound register.
priv: MRW
medeleg:
url: "/latest/machine.html#machine-trap-delegation-registers-medeleg-and-mideleg"
mmio: false
width: mxlen
desc: Machine Exception Delegation
number: 770
priv: MRW
sections:
machine:
- "/riscv-isa-manual/latest/machine.html#machine-trap-delegation-registers-medeleg-and-mideleg"
- "/riscv-isa-manual/latest/machine.html#machine-interrupt-registers-mip-and-mie"
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#sec:tinst-vals"
- "/riscv-isa-manual/latest/hypervisor.html#sec:hinterruptregs"
- "/riscv-isa-manual/latest/hypervisor.html#memory-management-fences"
n:
- "/riscv-isa-manual/latest/n.html#machine-trap-delegation-registers-medeleg-and-mideleg"
- "/riscv-isa-manual/latest/n.html#supervisor-trap-delegation-registers-sedeleg-and-sideleg"
- "/riscv-isa-manual/latest/n.html#other-csrs"
debug:
- "/riscv-debug-spec/latest/Sdtrig.html#memory-access-triggers"
menvcfg:
number: 778
desc: Machine environment configuration register.
priv: MRW
url: "/riscv-isa-manual/latest/machine.html#sec:mseccfg"
sections:
machine:
- "/riscv-isa-manual/latest/machine.html#sec:mseccfg"
menvcfgh:
number: 794
desc: Additional machine env. conf. register, RV32 only.
priv: MRW
url: "/riscv-isa-manual/latest/machine.html#sec:mseccfg"
sections:
machine:
- "/riscv-isa-manual/latest/machine.html#sec:mseccfg"
mepc:
url: "/riscv-isa-manual/latest/machine.html#machine-exception-program-counter-mepc"
mmio: false
width: mxlen
desc: Machine Exception Program Counter
number: 833
priv: MRW
sections:
machine:
- "/riscv-isa-manual/latest/machine.html#machine-exception-program-counter-mepc"
- "/riscv-isa-manual/latest/machine.html#machine-interrupt-registers-mip-and-mie"
- "/riscv-isa-manual/latest/machine.html#sec:mcause"
- "/riscv-isa-manual/latest/machine.html#machine-configuration-pointer-register-mconfigptr"
- "/riscv-isa-manual/latest/machine.html#sec:customsys"
- "/riscv-isa-manual/latest/machine.html#sec:pma"
hypervisor:
- "/riscv-isa-manual/latest/hypervisor.html#sec:tinst-vals"
n:
- "/riscv-isa-manual/latest/n.html#n-extension-instructions"
debug:
- "/riscv-debug-spec/latest/introduction.html#context"
- "/riscv-debug-spec/latest/Sdtrig.html#memory-access-triggers"
- "/riscv-debug-spec/latest/core_registers.html#debug-scratch-register-0-dscratch0-at-0x7b2"
mhartid: