/
asm5.go
2844 lines (2448 loc) · 67.6 KB
/
asm5.go
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// Inferno utils/5l/span.c
// http://code.google.com/p/inferno-os/source/browse/utils/5l/span.c
//
// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
// Portions Copyright © 1997-1999 Vita Nuova Limited
// Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com)
// Portions Copyright © 2004,2006 Bruce Ellis
// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
// Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others
// Portions Copyright © 2009 The Go Authors. All rights reserved.
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
package arm
import (
"cmd/internal/obj"
"fmt"
"log"
"math"
"sort"
)
type Optab struct {
as uint16
a1 uint8
a2 int8
a3 uint8
type_ uint8
size int8
param int16
flag int8
pcrelsiz uint8
}
type Oprang struct {
start []Optab
stop []Optab
}
type Opcross [32][2][32]uint8
const (
LFROM = 1 << 0
LTO = 1 << 1
LPOOL = 1 << 2
LPCREL = 1 << 3
)
var optab = []Optab{
/* struct Optab:
OPCODE, from, prog->reg, to, type,size,param,flag */
{obj.ATEXT, C_ADDR, C_NONE, C_TEXTSIZE, 0, 0, 0, 0, 0},
{AADD, C_REG, C_REG, C_REG, 1, 4, 0, 0, 0},
{AADD, C_REG, C_NONE, C_REG, 1, 4, 0, 0, 0},
{AMOVW, C_REG, C_NONE, C_REG, 1, 4, 0, 0, 0},
{AMVN, C_REG, C_NONE, C_REG, 1, 4, 0, 0, 0},
{ACMP, C_REG, C_REG, C_NONE, 1, 4, 0, 0, 0},
{AADD, C_RCON, C_REG, C_REG, 2, 4, 0, 0, 0},
{AADD, C_RCON, C_NONE, C_REG, 2, 4, 0, 0, 0},
{AMOVW, C_RCON, C_NONE, C_REG, 2, 4, 0, 0, 0},
{AMVN, C_RCON, C_NONE, C_REG, 2, 4, 0, 0, 0},
{ACMP, C_RCON, C_REG, C_NONE, 2, 4, 0, 0, 0},
{AADD, C_SHIFT, C_REG, C_REG, 3, 4, 0, 0, 0},
{AADD, C_SHIFT, C_NONE, C_REG, 3, 4, 0, 0, 0},
{AMVN, C_SHIFT, C_NONE, C_REG, 3, 4, 0, 0, 0},
{ACMP, C_SHIFT, C_REG, C_NONE, 3, 4, 0, 0, 0},
{AMOVW, C_RACON, C_NONE, C_REG, 4, 4, REGSP, 0, 0},
{AB, C_NONE, C_NONE, C_SBRA, 5, 4, 0, LPOOL, 0},
{ABL, C_NONE, C_NONE, C_SBRA, 5, 4, 0, 0, 0},
{ABX, C_NONE, C_NONE, C_SBRA, 74, 20, 0, 0, 0},
{ABEQ, C_NONE, C_NONE, C_SBRA, 5, 4, 0, 0, 0},
{ABEQ, C_RCON, C_NONE, C_SBRA, 5, 4, 0, 0, 0}, // prediction hinted form, hint ignored
{AB, C_NONE, C_NONE, C_ROREG, 6, 4, 0, LPOOL, 0},
{ABL, C_NONE, C_NONE, C_ROREG, 7, 4, 0, 0, 0},
{ABL, C_REG, C_NONE, C_ROREG, 7, 4, 0, 0, 0},
{ABX, C_NONE, C_NONE, C_ROREG, 75, 12, 0, 0, 0},
{ABXRET, C_NONE, C_NONE, C_ROREG, 76, 4, 0, 0, 0},
{ASLL, C_RCON, C_REG, C_REG, 8, 4, 0, 0, 0},
{ASLL, C_RCON, C_NONE, C_REG, 8, 4, 0, 0, 0},
{ASLL, C_REG, C_NONE, C_REG, 9, 4, 0, 0, 0},
{ASLL, C_REG, C_REG, C_REG, 9, 4, 0, 0, 0},
{ASWI, C_NONE, C_NONE, C_NONE, 10, 4, 0, 0, 0},
{ASWI, C_NONE, C_NONE, C_LOREG, 10, 4, 0, 0, 0},
{ASWI, C_NONE, C_NONE, C_LCON, 10, 4, 0, 0, 0},
{AWORD, C_NONE, C_NONE, C_LCON, 11, 4, 0, 0, 0},
{AWORD, C_NONE, C_NONE, C_LCONADDR, 11, 4, 0, 0, 0},
{AWORD, C_NONE, C_NONE, C_ADDR, 11, 4, 0, 0, 0},
{AWORD, C_NONE, C_NONE, C_TLS_LE, 103, 4, 0, 0, 0},
{AWORD, C_NONE, C_NONE, C_TLS_IE, 104, 4, 0, 0, 0},
{AMOVW, C_NCON, C_NONE, C_REG, 12, 4, 0, 0, 0},
{AMOVW, C_LCON, C_NONE, C_REG, 12, 4, 0, LFROM, 0},
{AMOVW, C_LCONADDR, C_NONE, C_REG, 12, 4, 0, LFROM | LPCREL, 4},
{AADD, C_NCON, C_REG, C_REG, 13, 8, 0, 0, 0},
{AADD, C_NCON, C_NONE, C_REG, 13, 8, 0, 0, 0},
{AMVN, C_NCON, C_NONE, C_REG, 13, 8, 0, 0, 0},
{ACMP, C_NCON, C_REG, C_NONE, 13, 8, 0, 0, 0},
{AADD, C_LCON, C_REG, C_REG, 13, 8, 0, LFROM, 0},
{AADD, C_LCON, C_NONE, C_REG, 13, 8, 0, LFROM, 0},
{AMVN, C_LCON, C_NONE, C_REG, 13, 8, 0, LFROM, 0},
{ACMP, C_LCON, C_REG, C_NONE, 13, 8, 0, LFROM, 0},
{AMOVB, C_REG, C_NONE, C_REG, 1, 4, 0, 0, 0},
{AMOVBS, C_REG, C_NONE, C_REG, 14, 8, 0, 0, 0},
{AMOVBU, C_REG, C_NONE, C_REG, 58, 4, 0, 0, 0},
{AMOVH, C_REG, C_NONE, C_REG, 1, 4, 0, 0, 0},
{AMOVHS, C_REG, C_NONE, C_REG, 14, 8, 0, 0, 0},
{AMOVHU, C_REG, C_NONE, C_REG, 14, 8, 0, 0, 0},
{AMUL, C_REG, C_REG, C_REG, 15, 4, 0, 0, 0},
{AMUL, C_REG, C_NONE, C_REG, 15, 4, 0, 0, 0},
{ADIV, C_REG, C_REG, C_REG, 16, 4, 0, 0, 0},
{ADIV, C_REG, C_NONE, C_REG, 16, 4, 0, 0, 0},
{AMULL, C_REG, C_REG, C_REGREG, 17, 4, 0, 0, 0},
{AMULA, C_REG, C_REG, C_REGREG2, 17, 4, 0, 0, 0},
{AMOVW, C_REG, C_NONE, C_SAUTO, 20, 4, REGSP, 0, 0},
{AMOVW, C_REG, C_NONE, C_SOREG, 20, 4, 0, 0, 0},
{AMOVB, C_REG, C_NONE, C_SAUTO, 20, 4, REGSP, 0, 0},
{AMOVB, C_REG, C_NONE, C_SOREG, 20, 4, 0, 0, 0},
{AMOVBS, C_REG, C_NONE, C_SAUTO, 20, 4, REGSP, 0, 0},
{AMOVBS, C_REG, C_NONE, C_SOREG, 20, 4, 0, 0, 0},
{AMOVBU, C_REG, C_NONE, C_SAUTO, 20, 4, REGSP, 0, 0},
{AMOVBU, C_REG, C_NONE, C_SOREG, 20, 4, 0, 0, 0},
{AMOVW, C_SAUTO, C_NONE, C_REG, 21, 4, REGSP, 0, 0},
{AMOVW, C_SOREG, C_NONE, C_REG, 21, 4, 0, 0, 0},
{AMOVBU, C_SAUTO, C_NONE, C_REG, 21, 4, REGSP, 0, 0},
{AMOVBU, C_SOREG, C_NONE, C_REG, 21, 4, 0, 0, 0},
{AMOVW, C_REG, C_NONE, C_LAUTO, 30, 8, REGSP, LTO, 0},
{AMOVW, C_REG, C_NONE, C_LOREG, 30, 8, 0, LTO, 0},
{AMOVW, C_REG, C_NONE, C_ADDR, 64, 8, 0, LTO | LPCREL, 4},
{AMOVB, C_REG, C_NONE, C_LAUTO, 30, 8, REGSP, LTO, 0},
{AMOVB, C_REG, C_NONE, C_LOREG, 30, 8, 0, LTO, 0},
{AMOVB, C_REG, C_NONE, C_ADDR, 64, 8, 0, LTO | LPCREL, 4},
{AMOVBS, C_REG, C_NONE, C_LAUTO, 30, 8, REGSP, LTO, 0},
{AMOVBS, C_REG, C_NONE, C_LOREG, 30, 8, 0, LTO, 0},
{AMOVBS, C_REG, C_NONE, C_ADDR, 64, 8, 0, LTO | LPCREL, 4},
{AMOVBU, C_REG, C_NONE, C_LAUTO, 30, 8, REGSP, LTO, 0},
{AMOVBU, C_REG, C_NONE, C_LOREG, 30, 8, 0, LTO, 0},
{AMOVBU, C_REG, C_NONE, C_ADDR, 64, 8, 0, LTO | LPCREL, 4},
{AMOVW, C_TLS_LE, C_NONE, C_REG, 101, 4, 0, LFROM, 0},
{AMOVW, C_TLS_IE, C_NONE, C_REG, 102, 8, 0, LFROM, 0},
{AMOVW, C_LAUTO, C_NONE, C_REG, 31, 8, REGSP, LFROM, 0},
{AMOVW, C_LOREG, C_NONE, C_REG, 31, 8, 0, LFROM, 0},
{AMOVW, C_ADDR, C_NONE, C_REG, 65, 8, 0, LFROM | LPCREL, 4},
{AMOVBU, C_LAUTO, C_NONE, C_REG, 31, 8, REGSP, LFROM, 0},
{AMOVBU, C_LOREG, C_NONE, C_REG, 31, 8, 0, LFROM, 0},
{AMOVBU, C_ADDR, C_NONE, C_REG, 65, 8, 0, LFROM | LPCREL, 4},
{AMOVW, C_LACON, C_NONE, C_REG, 34, 8, REGSP, LFROM, 0},
{AMOVW, C_PSR, C_NONE, C_REG, 35, 4, 0, 0, 0},
{AMOVW, C_REG, C_NONE, C_PSR, 36, 4, 0, 0, 0},
{AMOVW, C_RCON, C_NONE, C_PSR, 37, 4, 0, 0, 0},
{AMOVM, C_REGLIST, C_NONE, C_SOREG, 38, 4, 0, 0, 0},
{AMOVM, C_SOREG, C_NONE, C_REGLIST, 39, 4, 0, 0, 0},
{ASWPW, C_SOREG, C_REG, C_REG, 40, 4, 0, 0, 0},
{ARFE, C_NONE, C_NONE, C_NONE, 41, 4, 0, 0, 0},
{AMOVF, C_FREG, C_NONE, C_FAUTO, 50, 4, REGSP, 0, 0},
{AMOVF, C_FREG, C_NONE, C_FOREG, 50, 4, 0, 0, 0},
{AMOVF, C_FAUTO, C_NONE, C_FREG, 51, 4, REGSP, 0, 0},
{AMOVF, C_FOREG, C_NONE, C_FREG, 51, 4, 0, 0, 0},
{AMOVF, C_FREG, C_NONE, C_LAUTO, 52, 12, REGSP, LTO, 0},
{AMOVF, C_FREG, C_NONE, C_LOREG, 52, 12, 0, LTO, 0},
{AMOVF, C_LAUTO, C_NONE, C_FREG, 53, 12, REGSP, LFROM, 0},
{AMOVF, C_LOREG, C_NONE, C_FREG, 53, 12, 0, LFROM, 0},
{AMOVF, C_FREG, C_NONE, C_ADDR, 68, 8, 0, LTO | LPCREL, 4},
{AMOVF, C_ADDR, C_NONE, C_FREG, 69, 8, 0, LFROM | LPCREL, 4},
{AADDF, C_FREG, C_NONE, C_FREG, 54, 4, 0, 0, 0},
{AADDF, C_FREG, C_REG, C_FREG, 54, 4, 0, 0, 0},
{AMOVF, C_FREG, C_NONE, C_FREG, 54, 4, 0, 0, 0},
{AMOVW, C_REG, C_NONE, C_FCR, 56, 4, 0, 0, 0},
{AMOVW, C_FCR, C_NONE, C_REG, 57, 4, 0, 0, 0},
{AMOVW, C_SHIFT, C_NONE, C_REG, 59, 4, 0, 0, 0},
{AMOVBU, C_SHIFT, C_NONE, C_REG, 59, 4, 0, 0, 0},
{AMOVB, C_SHIFT, C_NONE, C_REG, 60, 4, 0, 0, 0},
{AMOVBS, C_SHIFT, C_NONE, C_REG, 60, 4, 0, 0, 0},
{AMOVW, C_REG, C_NONE, C_SHIFT, 61, 4, 0, 0, 0},
{AMOVB, C_REG, C_NONE, C_SHIFT, 61, 4, 0, 0, 0},
{AMOVBS, C_REG, C_NONE, C_SHIFT, 61, 4, 0, 0, 0},
{AMOVBU, C_REG, C_NONE, C_SHIFT, 61, 4, 0, 0, 0},
{AMOVH, C_REG, C_NONE, C_HAUTO, 70, 4, REGSP, 0, 0},
{AMOVH, C_REG, C_NONE, C_HOREG, 70, 4, 0, 0, 0},
{AMOVHS, C_REG, C_NONE, C_HAUTO, 70, 4, REGSP, 0, 0},
{AMOVHS, C_REG, C_NONE, C_HOREG, 70, 4, 0, 0, 0},
{AMOVHU, C_REG, C_NONE, C_HAUTO, 70, 4, REGSP, 0, 0},
{AMOVHU, C_REG, C_NONE, C_HOREG, 70, 4, 0, 0, 0},
{AMOVB, C_HAUTO, C_NONE, C_REG, 71, 4, REGSP, 0, 0},
{AMOVB, C_HOREG, C_NONE, C_REG, 71, 4, 0, 0, 0},
{AMOVBS, C_HAUTO, C_NONE, C_REG, 71, 4, REGSP, 0, 0},
{AMOVBS, C_HOREG, C_NONE, C_REG, 71, 4, 0, 0, 0},
{AMOVH, C_HAUTO, C_NONE, C_REG, 71, 4, REGSP, 0, 0},
{AMOVH, C_HOREG, C_NONE, C_REG, 71, 4, 0, 0, 0},
{AMOVHS, C_HAUTO, C_NONE, C_REG, 71, 4, REGSP, 0, 0},
{AMOVHS, C_HOREG, C_NONE, C_REG, 71, 4, 0, 0, 0},
{AMOVHU, C_HAUTO, C_NONE, C_REG, 71, 4, REGSP, 0, 0},
{AMOVHU, C_HOREG, C_NONE, C_REG, 71, 4, 0, 0, 0},
{AMOVH, C_REG, C_NONE, C_LAUTO, 72, 8, REGSP, LTO, 0},
{AMOVH, C_REG, C_NONE, C_LOREG, 72, 8, 0, LTO, 0},
{AMOVH, C_REG, C_NONE, C_ADDR, 94, 8, 0, LTO | LPCREL, 4},
{AMOVHS, C_REG, C_NONE, C_LAUTO, 72, 8, REGSP, LTO, 0},
{AMOVHS, C_REG, C_NONE, C_LOREG, 72, 8, 0, LTO, 0},
{AMOVHS, C_REG, C_NONE, C_ADDR, 94, 8, 0, LTO | LPCREL, 4},
{AMOVHU, C_REG, C_NONE, C_LAUTO, 72, 8, REGSP, LTO, 0},
{AMOVHU, C_REG, C_NONE, C_LOREG, 72, 8, 0, LTO, 0},
{AMOVHU, C_REG, C_NONE, C_ADDR, 94, 8, 0, LTO | LPCREL, 4},
{AMOVB, C_LAUTO, C_NONE, C_REG, 73, 8, REGSP, LFROM, 0},
{AMOVB, C_LOREG, C_NONE, C_REG, 73, 8, 0, LFROM, 0},
{AMOVB, C_ADDR, C_NONE, C_REG, 93, 8, 0, LFROM | LPCREL, 4},
{AMOVBS, C_LAUTO, C_NONE, C_REG, 73, 8, REGSP, LFROM, 0},
{AMOVBS, C_LOREG, C_NONE, C_REG, 73, 8, 0, LFROM, 0},
{AMOVBS, C_ADDR, C_NONE, C_REG, 93, 8, 0, LFROM | LPCREL, 4},
{AMOVH, C_LAUTO, C_NONE, C_REG, 73, 8, REGSP, LFROM, 0},
{AMOVH, C_LOREG, C_NONE, C_REG, 73, 8, 0, LFROM, 0},
{AMOVH, C_ADDR, C_NONE, C_REG, 93, 8, 0, LFROM | LPCREL, 4},
{AMOVHS, C_LAUTO, C_NONE, C_REG, 73, 8, REGSP, LFROM, 0},
{AMOVHS, C_LOREG, C_NONE, C_REG, 73, 8, 0, LFROM, 0},
{AMOVHS, C_ADDR, C_NONE, C_REG, 93, 8, 0, LFROM | LPCREL, 4},
{AMOVHU, C_LAUTO, C_NONE, C_REG, 73, 8, REGSP, LFROM, 0},
{AMOVHU, C_LOREG, C_NONE, C_REG, 73, 8, 0, LFROM, 0},
{AMOVHU, C_ADDR, C_NONE, C_REG, 93, 8, 0, LFROM | LPCREL, 4},
{ALDREX, C_SOREG, C_NONE, C_REG, 77, 4, 0, 0, 0},
{ASTREX, C_SOREG, C_REG, C_REG, 78, 4, 0, 0, 0},
{AMOVF, C_ZFCON, C_NONE, C_FREG, 80, 8, 0, 0, 0},
{AMOVF, C_SFCON, C_NONE, C_FREG, 81, 4, 0, 0, 0},
{ACMPF, C_FREG, C_REG, C_NONE, 82, 8, 0, 0, 0},
{ACMPF, C_FREG, C_NONE, C_NONE, 83, 8, 0, 0, 0},
{AMOVFW, C_FREG, C_NONE, C_FREG, 84, 4, 0, 0, 0},
{AMOVWF, C_FREG, C_NONE, C_FREG, 85, 4, 0, 0, 0},
{AMOVFW, C_FREG, C_NONE, C_REG, 86, 8, 0, 0, 0},
{AMOVWF, C_REG, C_NONE, C_FREG, 87, 8, 0, 0, 0},
{AMOVW, C_REG, C_NONE, C_FREG, 88, 4, 0, 0, 0},
{AMOVW, C_FREG, C_NONE, C_REG, 89, 4, 0, 0, 0},
{ATST, C_REG, C_NONE, C_NONE, 90, 4, 0, 0, 0},
{ALDREXD, C_SOREG, C_NONE, C_REG, 91, 4, 0, 0, 0},
{ASTREXD, C_SOREG, C_REG, C_REG, 92, 4, 0, 0, 0},
{APLD, C_SOREG, C_NONE, C_NONE, 95, 4, 0, 0, 0},
{obj.AUNDEF, C_NONE, C_NONE, C_NONE, 96, 4, 0, 0, 0},
{ACLZ, C_REG, C_NONE, C_REG, 97, 4, 0, 0, 0},
{AMULWT, C_REG, C_REG, C_REG, 98, 4, 0, 0, 0},
{AMULAWT, C_REG, C_REG, C_REGREG2, 99, 4, 0, 0, 0},
{obj.AUSEFIELD, C_ADDR, C_NONE, C_NONE, 0, 0, 0, 0, 0},
{obj.APCDATA, C_LCON, C_NONE, C_LCON, 0, 0, 0, 0, 0},
{obj.AFUNCDATA, C_LCON, C_NONE, C_ADDR, 0, 0, 0, 0, 0},
{obj.ANOP, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0, 0},
{obj.ADUFFZERO, C_NONE, C_NONE, C_SBRA, 5, 4, 0, 0, 0}, // same as ABL
{obj.ADUFFCOPY, C_NONE, C_NONE, C_SBRA, 5, 4, 0, 0, 0}, // same as ABL
{ADATABUNDLE, C_NONE, C_NONE, C_NONE, 100, 4, 0, 0, 0},
{ADATABUNDLEEND, C_NONE, C_NONE, C_NONE, 100, 0, 0, 0, 0},
{obj.AXXX, C_NONE, C_NONE, C_NONE, 0, 4, 0, 0, 0},
}
var pool struct {
start uint32
size uint32
extra uint32
}
var oprange [ALAST & obj.AMask]Oprang
var xcmp [C_GOK + 1][C_GOK + 1]uint8
var deferreturn *obj.LSym
// Note about encoding: Prog.scond holds the condition encoding,
// but XOR'ed with C_SCOND_XOR, so that C_SCOND_NONE == 0.
// The code that shifts the value << 28 has the responsibility
// for XORing with C_SCOND_XOR too.
// asmoutnacl assembles the instruction p. It replaces asmout for NaCl.
// It returns the total number of bytes put in out, and it can change
// p->pc if extra padding is necessary.
// In rare cases, asmoutnacl might split p into two instructions.
// origPC is the PC for this Prog (no padding is taken into account).
func asmoutnacl(ctxt *obj.Link, origPC int32, p *obj.Prog, o *Optab, out []uint32) int {
size := int(o.size)
// instruction specific
switch p.As {
default:
if out != nil {
asmout(ctxt, p, o, out)
}
case ADATABUNDLE, // align to 16-byte boundary
ADATABUNDLEEND: // zero width instruction, just to align next instruction to 16-byte boundary
p.Pc = (p.Pc + 15) &^ 15
if out != nil {
asmout(ctxt, p, o, out)
}
case obj.AUNDEF,
APLD:
size = 4
if out != nil {
switch p.As {
case obj.AUNDEF:
out[0] = 0xe7fedef0 // NACL_INSTR_ARM_ABORT_NOW (UDF #0xEDE0)
case APLD:
out[0] = 0xe1a01001 // (MOVW R1, R1)
}
}
case AB, ABL:
if p.To.Type != obj.TYPE_MEM {
if out != nil {
asmout(ctxt, p, o, out)
}
} else {
if p.To.Offset != 0 || size != 4 || p.To.Reg > REG_R15 || p.To.Reg < REG_R0 {
ctxt.Diag("unsupported instruction: %v", p)
}
if p.Pc&15 == 12 {
p.Pc += 4
}
if out != nil {
out[0] = ((uint32(p.Scond)&C_SCOND)^C_SCOND_XOR)<<28 | 0x03c0013f | (uint32(p.To.Reg)&15)<<12 | (uint32(p.To.Reg)&15)<<16 // BIC $0xc000000f, Rx
if p.As == AB {
out[1] = ((uint32(p.Scond)&C_SCOND)^C_SCOND_XOR)<<28 | 0x012fff10 | (uint32(p.To.Reg)&15)<<0 // BX Rx
} else { // ABL
out[1] = ((uint32(p.Scond)&C_SCOND)^C_SCOND_XOR)<<28 | 0x012fff30 | (uint32(p.To.Reg)&15)<<0 // BLX Rx
}
}
size = 8
}
// align the last instruction (the actual BL) to the last instruction in a bundle
if p.As == ABL {
if deferreturn == nil {
deferreturn = obj.Linklookup(ctxt, "runtime.deferreturn", 0)
}
if p.To.Sym == deferreturn {
p.Pc = ((int64(origPC) + 15) &^ 15) + 16 - int64(size)
} else {
p.Pc += (16 - ((p.Pc + int64(size)) & 15)) & 15
}
}
case ALDREX,
ALDREXD,
AMOVB,
AMOVBS,
AMOVBU,
AMOVD,
AMOVF,
AMOVH,
AMOVHS,
AMOVHU,
AMOVM,
AMOVW,
ASTREX,
ASTREXD:
if p.To.Type == obj.TYPE_REG && p.To.Reg == REG_R15 && p.From.Reg == REG_R13 { // MOVW.W x(R13), PC
if out != nil {
asmout(ctxt, p, o, out)
}
if size == 4 {
if out != nil {
// Note: 5c and 5g reg.c know that DIV/MOD smashes R12
// so that this return instruction expansion is valid.
out[0] = out[0] &^ 0x3000 // change PC to R12
out[1] = ((uint32(p.Scond)&C_SCOND)^C_SCOND_XOR)<<28 | 0x03ccc13f // BIC $0xc000000f, R12
out[2] = ((uint32(p.Scond)&C_SCOND)^C_SCOND_XOR)<<28 | 0x012fff1c // BX R12
}
size += 8
if (p.Pc+int64(size))&15 == 4 {
p.Pc += 4
}
break
} else {
// if the instruction used more than 4 bytes, then it must have used a very large
// offset to update R13, so we need to additionally mask R13.
if out != nil {
out[size/4-1] &^= 0x3000 // change PC to R12
out[size/4] = ((uint32(p.Scond)&C_SCOND)^C_SCOND_XOR)<<28 | 0x03cdd103 // BIC $0xc0000000, R13
out[size/4+1] = ((uint32(p.Scond)&C_SCOND)^C_SCOND_XOR)<<28 | 0x03ccc13f // BIC $0xc000000f, R12
out[size/4+2] = ((uint32(p.Scond)&C_SCOND)^C_SCOND_XOR)<<28 | 0x012fff1c // BX R12
}
// p->pc+size is only ok at 4 or 12 mod 16.
if (p.Pc+int64(size))%8 == 0 {
p.Pc += 4
}
size += 12
break
}
}
if p.To.Type == obj.TYPE_REG && p.To.Reg == REG_R15 {
ctxt.Diag("unsupported instruction (move to another register and use indirect jump instead): %v", p)
}
if p.To.Type == obj.TYPE_MEM && p.To.Reg == REG_R13 && (p.Scond&C_WBIT != 0) && size > 4 {
// function prolog with very large frame size: MOVW.W R14,-100004(R13)
// split it into two instructions:
// ADD $-100004, R13
// MOVW R14, 0(R13)
q := ctxt.NewProg()
p.Scond &^= C_WBIT
*q = *p
a := &p.To
var a2 *obj.Addr
if p.To.Type == obj.TYPE_MEM {
a2 = &q.To
} else {
a2 = &q.From
}
obj.Nocache(q)
obj.Nocache(p)
// insert q after p
q.Link = p.Link
p.Link = q
q.Pcond = nil
// make p into ADD $X, R13
p.As = AADD
p.From = *a
p.From.Reg = 0
p.From.Type = obj.TYPE_CONST
p.To = obj.Addr{}
p.To.Type = obj.TYPE_REG
p.To.Reg = REG_R13
// make q into p but load/store from 0(R13)
q.Spadj = 0
*a2 = obj.Addr{}
a2.Type = obj.TYPE_MEM
a2.Reg = REG_R13
a2.Sym = nil
a2.Offset = 0
size = int(oplook(ctxt, p).size)
break
}
if (p.To.Type == obj.TYPE_MEM && p.To.Reg != REG_R9) || // MOVW Rx, X(Ry), y != 9
(p.From.Type == obj.TYPE_MEM && p.From.Reg != REG_R9) { // MOVW X(Rx), Ry, x != 9
var a *obj.Addr
if p.To.Type == obj.TYPE_MEM {
a = &p.To
} else {
a = &p.From
}
reg := int(a.Reg)
if size == 4 {
// if addr.reg == 0, then it is probably load from x(FP) with small x, no need to modify.
if reg == 0 {
if out != nil {
asmout(ctxt, p, o, out)
}
} else {
if out != nil {
out[0] = ((uint32(p.Scond)&C_SCOND)^C_SCOND_XOR)<<28 | 0x03c00103 | (uint32(reg)&15)<<16 | (uint32(reg)&15)<<12 // BIC $0xc0000000, Rx
}
if p.Pc&15 == 12 {
p.Pc += 4
}
size += 4
if out != nil {
asmout(ctxt, p, o, out[1:])
}
}
break
} else {
// if a load/store instruction takes more than 1 word to implement, then
// we need to separate the instruction into two:
// 1. explicitly load the address into R11.
// 2. load/store from R11.
// This won't handle .W/.P, so we should reject such code.
if p.Scond&(C_PBIT|C_WBIT) != 0 {
ctxt.Diag("unsupported instruction (.P/.W): %v", p)
}
q := ctxt.NewProg()
*q = *p
var a2 *obj.Addr
if p.To.Type == obj.TYPE_MEM {
a2 = &q.To
} else {
a2 = &q.From
}
obj.Nocache(q)
obj.Nocache(p)
// insert q after p
q.Link = p.Link
p.Link = q
q.Pcond = nil
// make p into MOVW $X(R), R11
p.As = AMOVW
p.From = *a
p.From.Type = obj.TYPE_ADDR
p.To = obj.Addr{}
p.To.Type = obj.TYPE_REG
p.To.Reg = REG_R11
// make q into p but load/store from 0(R11)
*a2 = obj.Addr{}
a2.Type = obj.TYPE_MEM
a2.Reg = REG_R11
a2.Sym = nil
a2.Offset = 0
size = int(oplook(ctxt, p).size)
break
}
} else if out != nil {
asmout(ctxt, p, o, out)
}
}
// destination register specific
if p.To.Type == obj.TYPE_REG {
switch p.To.Reg {
case REG_R9:
ctxt.Diag("invalid instruction, cannot write to R9: %v", p)
case REG_R13:
if out != nil {
out[size/4] = 0xe3cdd103 // BIC $0xc0000000, R13
}
if (p.Pc+int64(size))&15 == 0 {
p.Pc += 4
}
size += 4
}
}
return size
}
func span5(ctxt *obj.Link, cursym *obj.LSym) {
var p *obj.Prog
var op *obj.Prog
p = cursym.Text
if p == nil || p.Link == nil { // handle external functions and ELF section symbols
return
}
if oprange[AAND&obj.AMask].start == nil {
buildop(ctxt)
}
ctxt.Cursym = cursym
ctxt.Autosize = int32(p.To.Offset + 4)
c := int32(0)
op = p
p = p.Link
var i int
var m int
var o *Optab
for ; p != nil || ctxt.Blitrl != nil; op, p = p, p.Link {
if p == nil {
if checkpool(ctxt, op, 0) {
p = op
continue
}
// can't happen: blitrl is not nil, but checkpool didn't flushpool
ctxt.Diag("internal inconsistency")
break
}
ctxt.Curp = p
p.Pc = int64(c)
o = oplook(ctxt, p)
if ctxt.Headtype != obj.Hnacl {
m = int(o.size)
} else {
m = asmoutnacl(ctxt, c, p, o, nil)
c = int32(p.Pc) // asmoutnacl might change pc for alignment
o = oplook(ctxt, p) // asmoutnacl might change p in rare cases
}
if m%4 != 0 || p.Pc%4 != 0 {
ctxt.Diag("!pc invalid: %v size=%d", p, m)
}
// must check literal pool here in case p generates many instructions
if ctxt.Blitrl != nil {
i = m
if checkpool(ctxt, op, i) {
p = op
continue
}
}
if m == 0 && (p.As != obj.AFUNCDATA && p.As != obj.APCDATA && p.As != ADATABUNDLEEND && p.As != obj.ANOP) {
ctxt.Diag("zero-width instruction\n%v", p)
continue
}
switch o.flag & (LFROM | LTO | LPOOL) {
case LFROM:
addpool(ctxt, p, &p.From)
case LTO:
addpool(ctxt, p, &p.To)
case LPOOL:
if p.Scond&C_SCOND == C_SCOND_NONE {
flushpool(ctxt, p, 0, 0)
}
}
if p.As == AMOVW && p.To.Type == obj.TYPE_REG && p.To.Reg == REGPC && p.Scond&C_SCOND == C_SCOND_NONE {
flushpool(ctxt, p, 0, 0)
}
c += int32(m)
}
cursym.Size = int64(c)
/*
* if any procedure is large enough to
* generate a large SBRA branch, then
* generate extra passes putting branches
* around jmps to fix. this is rare.
*/
times := 0
var bflag int
var opc int32
var out [6 + 3]uint32
for {
if ctxt.Debugvlog != 0 {
fmt.Fprintf(ctxt.Bso, "%5.2f span1\n", obj.Cputime())
}
bflag = 0
c = 0
times++
cursym.Text.Pc = 0 // force re-layout the code.
for p = cursym.Text; p != nil; p = p.Link {
ctxt.Curp = p
o = oplook(ctxt, p)
if int64(c) > p.Pc {
p.Pc = int64(c)
}
/* very large branches
if(o->type == 6 && p->pcond) {
otxt = p->pcond->pc - c;
if(otxt < 0)
otxt = -otxt;
if(otxt >= (1L<<17) - 10) {
q = emallocz(sizeof(Prog));
q->link = p->link;
p->link = q;
q->as = AB;
q->to.type = TYPE_BRANCH;
q->pcond = p->pcond;
p->pcond = q;
q = emallocz(sizeof(Prog));
q->link = p->link;
p->link = q;
q->as = AB;
q->to.type = TYPE_BRANCH;
q->pcond = q->link->link;
bflag = 1;
}
}
*/
opc = int32(p.Pc)
if ctxt.Headtype != obj.Hnacl {
m = int(o.size)
} else {
m = asmoutnacl(ctxt, c, p, o, nil)
}
if p.Pc != int64(opc) {
bflag = 1
}
//print("%v pc changed %d to %d in iter. %d\n", p, opc, (int32)p->pc, times);
c = int32(p.Pc + int64(m))
if m%4 != 0 || p.Pc%4 != 0 {
ctxt.Diag("pc invalid: %v size=%d", p, m)
}
if m/4 > len(out) {
ctxt.Diag("instruction size too large: %d > %d", m/4, len(out))
}
if m == 0 && (p.As != obj.AFUNCDATA && p.As != obj.APCDATA && p.As != ADATABUNDLEEND && p.As != obj.ANOP) {
if p.As == obj.ATEXT {
ctxt.Autosize = int32(p.To.Offset + 4)
continue
}
ctxt.Diag("zero-width instruction\n%v", p)
continue
}
}
cursym.Size = int64(c)
if bflag == 0 {
break
}
}
if c%4 != 0 {
ctxt.Diag("sym->size=%d, invalid", c)
}
/*
* lay out the code. all the pc-relative code references,
* even cross-function, are resolved now;
* only data references need to be relocated.
* with more work we could leave cross-function
* code references to be relocated too, and then
* perhaps we'd be able to parallelize the span loop above.
*/
p = cursym.Text
ctxt.Autosize = int32(p.To.Offset + 4)
obj.Symgrow(ctxt, cursym, cursym.Size)
bp := cursym.P
c = int32(p.Pc) // even p->link might need extra padding
var v int
for p = p.Link; p != nil; p = p.Link {
ctxt.Pc = p.Pc
ctxt.Curp = p
o = oplook(ctxt, p)
opc = int32(p.Pc)
if ctxt.Headtype != obj.Hnacl {
asmout(ctxt, p, o, out[:])
m = int(o.size)
} else {
m = asmoutnacl(ctxt, c, p, o, out[:])
if int64(opc) != p.Pc {
ctxt.Diag("asmoutnacl broken: pc changed (%d->%d) in last stage: %v", opc, int32(p.Pc), p)
}
}
if m%4 != 0 || p.Pc%4 != 0 {
ctxt.Diag("final stage: pc invalid: %v size=%d", p, m)
}
if int64(c) > p.Pc {
ctxt.Diag("PC padding invalid: want %#d, has %#d: %v", p.Pc, c, p)
}
for int64(c) != p.Pc {
// emit 0xe1a00000 (MOVW R0, R0)
bp[0] = 0x00
bp = bp[1:]
bp[0] = 0x00
bp = bp[1:]
bp[0] = 0xa0
bp = bp[1:]
bp[0] = 0xe1
bp = bp[1:]
c += 4
}
for i = 0; i < m/4; i++ {
v = int(out[i])
bp[0] = byte(v)
bp = bp[1:]
bp[0] = byte(v >> 8)
bp = bp[1:]
bp[0] = byte(v >> 16)
bp = bp[1:]
bp[0] = byte(v >> 24)
bp = bp[1:]
}
c += int32(m)
}
}
/*
* when the first reference to the literal pool threatens
* to go out of range of a 12-bit PC-relative offset,
* drop the pool now, and branch round it.
* this happens only in extended basic blocks that exceed 4k.
*/
func checkpool(ctxt *obj.Link, p *obj.Prog, sz int) bool {
if pool.size >= 0xff0 || immaddr(int32((p.Pc+int64(sz)+4)+4+int64(12+pool.size)-int64(pool.start+8))) == 0 {
return flushpool(ctxt, p, 1, 0)
} else if p.Link == nil {
return flushpool(ctxt, p, 2, 0)
}
return false
}
func flushpool(ctxt *obj.Link, p *obj.Prog, skip int, force int) bool {
if ctxt.Blitrl != nil {
if skip != 0 {
if false && skip == 1 {
fmt.Printf("note: flush literal pool at %x: len=%d ref=%x\n", uint64(p.Pc+4), pool.size, pool.start)
}
q := ctxt.NewProg()
q.As = AB
q.To.Type = obj.TYPE_BRANCH
q.Pcond = p.Link
q.Link = ctxt.Blitrl
q.Lineno = p.Lineno
ctxt.Blitrl = q
} else if force == 0 && (p.Pc+int64(12+pool.size)-int64(pool.start) < 2048) { // 12 take into account the maximum nacl literal pool alignment padding size
return false
}
if ctxt.Headtype == obj.Hnacl && pool.size%16 != 0 {
// if pool is not multiple of 16 bytes, add an alignment marker
q := ctxt.NewProg()
q.As = ADATABUNDLEEND
ctxt.Elitrl.Link = q
ctxt.Elitrl = q
}
// The line number for constant pool entries doesn't really matter.
// We set it to the line number of the preceding instruction so that
// there are no deltas to encode in the pc-line tables.
for q := ctxt.Blitrl; q != nil; q = q.Link {
q.Lineno = p.Lineno
}
ctxt.Elitrl.Link = p.Link
p.Link = ctxt.Blitrl
ctxt.Blitrl = nil /* BUG: should refer back to values until out-of-range */
ctxt.Elitrl = nil
pool.size = 0
pool.start = 0
pool.extra = 0
return true
}
return false
}
func addpool(ctxt *obj.Link, p *obj.Prog, a *obj.Addr) {
var t obj.Prog
c := aclass(ctxt, a)
t.Ctxt = ctxt
t.As = AWORD
switch c {
default:
t.To.Offset = a.Offset
t.To.Sym = a.Sym
t.To.Type = a.Type
t.To.Name = a.Name
if ctxt.Flag_shared != 0 && t.To.Sym != nil {
t.Rel = p
}
case C_SROREG,
C_LOREG,
C_ROREG,
C_FOREG,
C_SOREG,
C_HOREG,
C_FAUTO,
C_SAUTO,
C_LAUTO,
C_LACON:
t.To.Type = obj.TYPE_CONST
t.To.Offset = ctxt.Instoffset
}
if t.Rel == nil {
for q := ctxt.Blitrl; q != nil; q = q.Link { /* could hash on t.t0.offset */
if q.Rel == nil && q.To == t.To {
p.Pcond = q
return
}
}
}
if ctxt.Headtype == obj.Hnacl && pool.size%16 == 0 {
// start a new data bundle
q := ctxt.NewProg()
q.As = ADATABUNDLE
q.Pc = int64(pool.size)
pool.size += 4
if ctxt.Blitrl == nil {
ctxt.Blitrl = q
pool.start = uint32(p.Pc)
} else {
ctxt.Elitrl.Link = q
}
ctxt.Elitrl = q
}
q := ctxt.NewProg()
*q = t
q.Pc = int64(pool.size)
if ctxt.Blitrl == nil {
ctxt.Blitrl = q
pool.start = uint32(p.Pc)
} else {
ctxt.Elitrl.Link = q
}
ctxt.Elitrl = q
pool.size += 4
p.Pcond = q
}
func regoff(ctxt *obj.Link, a *obj.Addr) int32 {
ctxt.Instoffset = 0
aclass(ctxt, a)
return int32(ctxt.Instoffset)
}
func immrot(v uint32) int32 {
for i := 0; i < 16; i++ {
if v&^0xff == 0 {
return int32(uint32(int32(i)<<8) | v | 1<<25)
}
v = v<<2 | v>>30
}
return 0
}
func immaddr(v int32) int32 {
if v >= 0 && v <= 0xfff {
return v&0xfff | 1<<24 | 1<<23 /* pre indexing */ /* pre indexing, up */
}
if v >= -0xfff && v < 0 {
return -v&0xfff | 1<<24 /* pre indexing */
}
return 0
}
func immfloat(v int32) bool {
return v&0xC03 == 0 /* offset will fit in floating-point load/store */
}
func immhalf(v int32) bool {
if v >= 0 && v <= 0xff {
return v|1<<24|1<<23 != 0 /* pre indexing */ /* pre indexing, up */
}
if v >= -0xff && v < 0 {
return -v&0xff|1<<24 != 0 /* pre indexing */
}
return false
}
func aclass(ctxt *obj.Link, a *obj.Addr) int {
switch a.Type {
case obj.TYPE_NONE:
return C_NONE
case obj.TYPE_REG:
ctxt.Instoffset = 0
if REG_R0 <= a.Reg && a.Reg <= REG_R15 {
return C_REG
}
if REG_F0 <= a.Reg && a.Reg <= REG_F15 {
return C_FREG
}
if a.Reg == REG_FPSR || a.Reg == REG_FPCR {
return C_FCR
}
if a.Reg == REG_CPSR || a.Reg == REG_SPSR {
return C_PSR
}
return C_GOK
case obj.TYPE_REGREG:
return C_REGREG