VHDL: Cannot export standard lib circuits with unconnected outputs

[wmurbina]

VHDL bugs.
When I try to export a circuit with a register to VHDL, I get the following error. This is because in the flip-flop D Q' is not connected.

[flandreas]

@wmurbina Thank you for reporting this.

The restriction to all pins being connected is intentional in VHDL export. However, I wasn't aware that the standard library has circuits with unconnected outputs. I have to think about how to deal with this..

[flandreas]

Relaxed restriction to "unconnected input pins" instead of "unconnected pins". Unconnected output pins are now allowed.