VHDL recommendation: Entity names

[wmurbina]

When I try to export to VHDL a circuit the entity should have the same name as the circuit.

For example:

instead of main it should be Half_adder.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- Half_adder
entity main is
port (
A: in std_logic;
B: in std_logic;
S: out std_logic;
C: out std_logic);
end main;

architecture Behavioral of main is
begin
S <= (A XOR B);
C <= (A AND B);
end Behavioral;

[flandreas]

@wmurbina Can you please explain why this is an issue for you? Does "main" conflict with something else, or what is your use case?

[wmurbina]

The problem is when the generated code is to be used in other software such as Xilinx's Vivado.

It will be difficult to identify when you have several files.

Another thing that I have identified that is confusing is the names given to the entities when exporting in VHDL, these are too long. It could be improved if you put the name of the subcircuit (or name of the block of the standard library).

I attach an example of what I am trying to explain.

[flandreas]

Ok, I see, thank you!

The current naming scheme based on "main" and UUIDs for the subcircuits was straight-forward, and it ensured unique names. But I see your point.

So I will change it so that the entities are named like the circuits, adjusting them as needed to comply with VHDL naming syntax rules and uniqueness.