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z80.h
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z80.h
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#pragma once
/*#
# z80.h
A cycle-stepped Z80 emulator in a C header.
Do this:
~~~~C
#define CHIPS_IMPL
~~~~
before you include this file in *one* C or C++ file to create the
implementation.
Optionally provide
~~~C
#define CHIPS_ASSERT(x) your_own_asset_macro(x)
~~~
## Emulated Pins
***********************************
* +-----------+ *
* M1 <---| |---> A0 *
* MREQ <---| |---> A1 *
* IORQ <---| |---> A2 *
* RD <---| |---> .. *
* WR <---| Z80 |---> A15 *
* HALT <---| | *
* WAIT --->| |<--> D0 *
* INT --->| |<--> D1 *
* NMI --->| |<--> ... *
* RFSH <---| |<--> D7 *
* +-----------+ *
***********************************
## Functions
~~~C
uint64_t z80_init(z80_t* cpu);
~~~
Initializes a new z80_t instance, returns initial pin mask to start
execution at address 0.
~~~C
uint64_t z80_reset(z80_t* cpu)
~~~
Resets a z80_t instance, returns pin mask to start execution at
address 0.
~~~C
uint64_t z80_tick(z80_t* cpu, uint64_t pins)
~~~
Step the z80_t instance for one clock cycle.
~~~C
uint64_t z80_prefetch(z80_t* cpu, uint16_t new_pc)
~~~
Call this function to force execution to start at a specific
PC. Use the returned pin mask as argument into the next z80_tick() call.
~~~C
bool z80_opdone(z80_t* cpu)
~~~
Helper function to detect whether the z80_t instance has completed
an instruction.
## HOWTO
Initialize a new z80_t instance and start ticking it:
~~~C
z80_t cpu;
uint64_t pins = z80_init(&cpu);
while (!done) {
pins = z80_tick(&cpu, pins);
}
~~~
Since there is no memory attached yet, the CPU will simply run whatever opcode
bytes are present on the data bus (in this case the data bus is zero, so the CPU
just runs throught the same NOP over and over).
Next, add some memory and inspect and modify the pin mask to handle memory accesses:
~~~C
uint8_t mem[(1<<16)] = {0};
z80_t cpu;
uint64_t pins = z80_init(&cpu);
while (!done) {
pins = z80_tick(&cpu, pins);
if (pins & Z80_MREQ) {
const uint16_t addr = Z80_GET_ADDR(pins);
if (pins & Z80_RD) {
uint8_t data = mem[addr];
Z80_SET_DATA(pins, data);
}
else if (pins & Z80_WR) {
uint8_t data = Z80_GET_DATA(pins);
mem[addr] = data;
}
}
}
~~~
The CPU will now run through the whole address space executing NOPs (because the memory is
filled with 0s instead of a valid program). If there would be a valid Z80 program at memory
address 0, this would be executed instead.
IO requests are handled the same as memory requests, but instead of the MREQ pin, the
IORQ pin must be checked:
~~~C
uint8_t mem[(1<<16)] = {0};
z80_t cpu;
uint64_t pins = z80_init(&cpu);
while (!done) {
pins = z80_tick(&cpu, pins);
if (pins & Z80_MREQ) {
const uint16_t addr = Z80_GET_ADDR(pins);
if (pins & Z80_RD) {
uint8_t data = mem[addr];
Z80_SET_DATA(pins, data);
}
else if (pins & Z80_WR) {
uint8_t data = Z80_GET_DATA(pins);
mem[addr] = data;
}
}
else if (pins & Z80_IORQ) {
const uint16_t port = Z80_GET_ADDR(pins);
if (pins & Z80_RD) {
// handle IO input request at port
...
}
else if (pins & Z80_WR) {
// handle IO output request at port
...
}
}
}
~~~
Handle interrupt acknowledge cycles by checking for Z80_IORQ|Z80_M1:
~~~C
uint8_t mem[(1<<16)] = {0};
z80_t cpu;
uint64_t pins = z80_init(&cpu);
while (!done) {
pins = z80_tick(&cpu, pins);
if (pins & Z80_MREQ) {
const uint16_t addr = Z80_GET_ADDR(pins);
if (pins & Z80_RD) {
uint8_t data = mem[addr];
Z80_SET_DATA(pins, data);
}
else if (pins & Z80_WR) {
uint8_t data = Z80_GET_DATA(pins);
mem[addr] = data;
}
}
else if (pins & Z80_IORQ) {
const uint16_t addr = Z80_GET_ADDR(pins);
if (pins & Z80_M1) {
// an interrupt acknowledge cycle, depending on the emulated system,
// put either an instruction byte, or an interrupt vector on the data bus
Z80_SET_DATA(pins, opcode_or_intvec);
}
else if (pins & Z80_RD) {
// handle IO input request at port `addr`
...
}
else if (pins & Z80_WR) {
// handle IO output request at port `addr`
...
}
}
}
~~~
To request an interrupt, or inject a wait state just set the respective pin
(Z80_INT, Z80_NMI, Z80_WAIT), don't forget to clear the pin again later (the
details on when those pins are set and cleared depend heavily on the
emulated system).
!!! note
NOTE: The Z80_RES pin is currently not emulated. Instead call the `z80_reset()` function.
To emulate a whole computer system, add the per-tick code for the rest of the system to the
basic ticking code above.
If the emulated system uses the Z80 daisychain interrupt protocol (for instance when using
the Z80 family chips like the PIO or CTC), tick those chips in interrupt priority order and
set the Z80_IEIO pin before the highest priority chip in the daisychain is ticked:
~~~C
...
while (!done) {
pins = z80_tick(&cpu, pins);
...
// tick Z80 family chips in 'daisychain order':
pins |= Z80_IEIO;
...
pins = z80ctc_tick(&ctc, pins);
...
pins = z80pio_tick(&pio, pins);
...
// the Z80_INT pin will now be set if any of the chips wants to issue an interrupt request
}
~~~
#*/
/*
zlib/libpng license
Copyright (c) 2021 Andre Weissflog
This software is provided 'as-is', without any express or implied warranty.
In no event will the authors be held liable for any damages arising from the
use of this software.
Permission is granted to anyone to use this software for any purpose,
including commercial applications, and to alter it and redistribute it
freely, subject to the following restrictions:
1. The origin of this software must not be misrepresented; you must not
claim that you wrote the original software. If you use this software in a
product, an acknowledgment in the product documentation would be
appreciated but is not required.
2. Altered source versions must be plainly marked as such, and must not
be misrepresented as being the original software.
3. This notice may not be removed or altered from any source
distribution.
*/
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
// address pins
#define Z80_PIN_A0 (0)
#define Z80_PIN_A1 (1)
#define Z80_PIN_A2 (2)
#define Z80_PIN_A3 (3)
#define Z80_PIN_A4 (4)
#define Z80_PIN_A5 (5)
#define Z80_PIN_A6 (6)
#define Z80_PIN_A7 (7)
#define Z80_PIN_A8 (8)
#define Z80_PIN_A9 (9)
#define Z80_PIN_A10 (10)
#define Z80_PIN_A11 (11)
#define Z80_PIN_A12 (12)
#define Z80_PIN_A13 (13)
#define Z80_PIN_A14 (14)
#define Z80_PIN_A15 (15)
// data pins
#define Z80_PIN_D0 (16)
#define Z80_PIN_D1 (17)
#define Z80_PIN_D2 (18)
#define Z80_PIN_D3 (19)
#define Z80_PIN_D4 (20)
#define Z80_PIN_D5 (21)
#define Z80_PIN_D6 (22)
#define Z80_PIN_D7 (23)
// control pins
#define Z80_PIN_M1 (24) // machine cycle 1
#define Z80_PIN_MREQ (25) // memory request
#define Z80_PIN_IORQ (26) // input/output request
#define Z80_PIN_RD (27) // read
#define Z80_PIN_WR (28) // write
#define Z80_PIN_HALT (29) // halt state
#define Z80_PIN_INT (30) // interrupt request
#define Z80_PIN_RES (31) // reset requested
#define Z80_PIN_NMI (32) // non-maskable interrupt
#define Z80_PIN_WAIT (33) // wait requested
#define Z80_PIN_RFSH (34) // refresh
// virtual pins (for interrupt daisy chain protocol)
#define Z80_PIN_IEIO (37) // unified daisy chain 'Interrupt Enable In+Out'
#define Z80_PIN_RETI (38) // cpu has decoded a RETI instruction
// pin bit masks
#define Z80_A0 (1ULL<<Z80_PIN_A0)
#define Z80_A1 (1ULL<<Z80_PIN_A1)
#define Z80_A2 (1ULL<<Z80_PIN_A2)
#define Z80_A3 (1ULL<<Z80_PIN_A3)
#define Z80_A4 (1ULL<<Z80_PIN_A4)
#define Z80_A5 (1ULL<<Z80_PIN_A5)
#define Z80_A6 (1ULL<<Z80_PIN_A6)
#define Z80_A7 (1ULL<<Z80_PIN_A7)
#define Z80_A8 (1ULL<<Z80_PIN_A8)
#define Z80_A9 (1ULL<<Z80_PIN_A9)
#define Z80_A10 (1ULL<<Z80_PIN_A10)
#define Z80_A11 (1ULL<<Z80_PIN_A11)
#define Z80_A12 (1ULL<<Z80_PIN_A12)
#define Z80_A13 (1ULL<<Z80_PIN_A13)
#define Z80_A14 (1ULL<<Z80_PIN_A14)
#define Z80_A15 (1ULL<<Z80_PIN_A15)
#define Z80_D0 (1ULL<<Z80_PIN_D0)
#define Z80_D1 (1ULL<<Z80_PIN_D1)
#define Z80_D2 (1ULL<<Z80_PIN_D2)
#define Z80_D3 (1ULL<<Z80_PIN_D3)
#define Z80_D4 (1ULL<<Z80_PIN_D4)
#define Z80_D5 (1ULL<<Z80_PIN_D5)
#define Z80_D6 (1ULL<<Z80_PIN_D6)
#define Z80_D7 (1ULL<<Z80_PIN_D7)
#define Z80_M1 (1ULL<<Z80_PIN_M1)
#define Z80_MREQ (1ULL<<Z80_PIN_MREQ)
#define Z80_IORQ (1ULL<<Z80_PIN_IORQ)
#define Z80_RD (1ULL<<Z80_PIN_RD)
#define Z80_WR (1ULL<<Z80_PIN_WR)
#define Z80_HALT (1ULL<<Z80_PIN_HALT)
#define Z80_INT (1ULL<<Z80_PIN_INT)
#define Z80_RES (1ULL<<Z80_PIN_RES)
#define Z80_NMI (1ULL<<Z80_PIN_NMI)
#define Z80_WAIT (1ULL<<Z80_PIN_WAIT)
#define Z80_RFSH (1ULL<<Z80_PIN_RFSH)
#define Z80_IEIO (1ULL<<Z80_PIN_IEIO)
#define Z80_RETI (1ULL<<Z80_PIN_RETI)
#define Z80_CTRL_PIN_MASK (Z80_M1|Z80_MREQ|Z80_IORQ|Z80_RD|Z80_WR|Z80_RFSH)
#define Z80_PIN_MASK ((1ULL<<40)-1)
// pin access helper macros
#define Z80_MAKE_PINS(ctrl, addr, data) ((ctrl)|((data&0xFF)<<16)|((addr)&0xFFFFULL))
#define Z80_GET_ADDR(p) ((uint16_t)(p))
#define Z80_SET_ADDR(p,a) {p=((p)&~0xFFFF)|((a)&0xFFFF);}
#define Z80_GET_DATA(p) ((uint8_t)((p)>>16))
#define Z80_SET_DATA(p,d) {p=((p)&~0xFF0000ULL)|(((d)<<16)&0xFF0000ULL);}
// status flags
#define Z80_CF (1<<0) // carry
#define Z80_NF (1<<1) // add/subtract
#define Z80_VF (1<<2) // parity/overflow
#define Z80_PF Z80_VF
#define Z80_XF (1<<3) // undocumented bit 3
#define Z80_HF (1<<4) // half carry
#define Z80_YF (1<<5) // undocumented bit 5
#define Z80_ZF (1<<6) // zero
#define Z80_SF (1<<7) // sign
// CPU state
typedef struct {
uint16_t step; // the currently active decoder step
uint16_t addr; // effective address for (HL),(IX+d),(IY+d)
uint8_t dlatch; // temporary store for data bus value
uint8_t opcode; // current opcode
uint8_t hlx_idx; // index into hlx[] for mapping hl to ix or iy (0: hl, 1: ix, 2: iy)
bool prefix_active; // true if any prefix currently active (only needed in z80_opdone())
uint64_t pins; // last pin state, used for NMI detection
uint64_t int_bits; // track INT and NMI state
union { struct { uint8_t pcl; uint8_t pch; }; uint16_t pc; };
// NOTE: These unions are fine in C, but not C++.
union { struct { uint8_t f; uint8_t a; }; uint16_t af; };
union { struct { uint8_t c; uint8_t b; }; uint16_t bc; };
union { struct { uint8_t e; uint8_t d; }; uint16_t de; };
union {
struct {
union { struct { uint8_t l; uint8_t h; }; uint16_t hl; };
union { struct { uint8_t ixl; uint8_t ixh; }; uint16_t ix; };
union { struct { uint8_t iyl; uint8_t iyh; }; uint16_t iy; };
};
struct { union { struct { uint8_t l; uint8_t h; }; uint16_t hl; }; } hlx[3];
};
union { struct { uint8_t wzl; uint8_t wzh; }; uint16_t wz; };
union { struct { uint8_t spl; uint8_t sph; }; uint16_t sp; };
union { struct { uint8_t r; uint8_t i; }; uint16_t ir; };
uint16_t af2, bc2, de2, hl2; // shadow register bank
uint8_t im;
bool iff1, iff2;
} z80_t;
// initialize a new Z80 instance and return initial pin mask
uint64_t z80_init(z80_t* cpu);
// immediately put Z80 into reset state
uint64_t z80_reset(z80_t* cpu);
// execute one tick, return new pin mask
uint64_t z80_tick(z80_t* cpu, uint64_t pins);
// force execution to continue at address 'new_pc'
uint64_t z80_prefetch(z80_t* cpu, uint16_t new_pc);
// return true when full instruction has finished
bool z80_opdone(z80_t* cpu);
#ifdef __cplusplus
} // extern C
#endif
//-- IMPLEMENTATION ------------------------------------------------------------
#ifdef CHIPS_IMPL
#include <string.h> // memset
#ifndef CHIPS_ASSERT
#include <assert.h>
#define CHIPS_ASSERT(c) assert(c)
#endif
#if defined(__GNUC__)
#define _Z80_UNREACHABLE __builtin_unreachable()
#elif defined(_MSC_VER)
#define _Z80_UNREACHABLE __assume(0)
#else
#define _Z80_UNREACHABLE
#endif
// values for hlx_idx for mapping HL, IX or IY, used as index into hlx[]
#define _Z80_MAP_HL (0)
#define _Z80_MAP_IX (1)
#define _Z80_MAP_IY (2)
uint64_t z80_init(z80_t* cpu) {
CHIPS_ASSERT(cpu);
// initial state as described in 'The Undocumented Z80 Documented'
memset(cpu, 0, sizeof(z80_t));
cpu->af = cpu->bc = cpu->de = cpu->hl = 0xFFFF;
cpu->wz = cpu->sp = cpu->ix = cpu->iy = 0xFFFF;
cpu->af2 = cpu->bc2 = cpu->de2 = cpu->hl2 = 0xFFFF;
return z80_prefetch(cpu, 0x0000);
}
uint64_t z80_reset(z80_t* cpu) {
// reset state as described in 'The Undocumented Z80 Documented'
memset(cpu, 0, sizeof(z80_t));
cpu->af = cpu->bc = cpu->de = cpu->hl = 0xFFFF;
cpu->wz = cpu->sp = cpu->ix = cpu->iy = 0xFFFF;
cpu->af2 = cpu->bc2 = cpu->de2 = cpu->hl2 = 0xFFFF;
return z80_prefetch(cpu, 0x0000);
}
bool z80_opdone(z80_t* cpu) {
// because of the overlapped cycle, the result of the previous
// instruction is only available in M1/T2
return ((cpu->pins & (Z80_M1|Z80_RD)) == (Z80_M1|Z80_RD)) && !cpu->prefix_active;
}
static inline uint64_t _z80_halt(z80_t* cpu, uint64_t pins) {
cpu->pc--;
return pins | Z80_HALT;
}
// sign+zero+parity lookup table
static const uint8_t _z80_szp_flags[256] = {
0x44,0x00,0x00,0x04,0x00,0x04,0x04,0x00,0x08,0x0c,0x0c,0x08,0x0c,0x08,0x08,0x0c,
0x00,0x04,0x04,0x00,0x04,0x00,0x00,0x04,0x0c,0x08,0x08,0x0c,0x08,0x0c,0x0c,0x08,
0x20,0x24,0x24,0x20,0x24,0x20,0x20,0x24,0x2c,0x28,0x28,0x2c,0x28,0x2c,0x2c,0x28,
0x24,0x20,0x20,0x24,0x20,0x24,0x24,0x20,0x28,0x2c,0x2c,0x28,0x2c,0x28,0x28,0x2c,
0x00,0x04,0x04,0x00,0x04,0x00,0x00,0x04,0x0c,0x08,0x08,0x0c,0x08,0x0c,0x0c,0x08,
0x04,0x00,0x00,0x04,0x00,0x04,0x04,0x00,0x08,0x0c,0x0c,0x08,0x0c,0x08,0x08,0x0c,
0x24,0x20,0x20,0x24,0x20,0x24,0x24,0x20,0x28,0x2c,0x2c,0x28,0x2c,0x28,0x28,0x2c,
0x20,0x24,0x24,0x20,0x24,0x20,0x20,0x24,0x2c,0x28,0x28,0x2c,0x28,0x2c,0x2c,0x28,
0x80,0x84,0x84,0x80,0x84,0x80,0x80,0x84,0x8c,0x88,0x88,0x8c,0x88,0x8c,0x8c,0x88,
0x84,0x80,0x80,0x84,0x80,0x84,0x84,0x80,0x88,0x8c,0x8c,0x88,0x8c,0x88,0x88,0x8c,
0xa4,0xa0,0xa0,0xa4,0xa0,0xa4,0xa4,0xa0,0xa8,0xac,0xac,0xa8,0xac,0xa8,0xa8,0xac,
0xa0,0xa4,0xa4,0xa0,0xa4,0xa0,0xa0,0xa4,0xac,0xa8,0xa8,0xac,0xa8,0xac,0xac,0xa8,
0x84,0x80,0x80,0x84,0x80,0x84,0x84,0x80,0x88,0x8c,0x8c,0x88,0x8c,0x88,0x88,0x8c,
0x80,0x84,0x84,0x80,0x84,0x80,0x80,0x84,0x8c,0x88,0x88,0x8c,0x88,0x8c,0x8c,0x88,
0xa0,0xa4,0xa4,0xa0,0xa4,0xa0,0xa0,0xa4,0xac,0xa8,0xa8,0xac,0xa8,0xac,0xac,0xa8,
0xa4,0xa0,0xa0,0xa4,0xa0,0xa4,0xa4,0xa0,0xa8,0xac,0xac,0xa8,0xac,0xa8,0xa8,0xac,
};
static inline uint8_t _z80_sz_flags(uint8_t val) {
return (val != 0) ? (val & Z80_SF) : Z80_ZF;
}
static inline uint8_t _z80_szyxch_flags(uint8_t acc, uint8_t val, uint32_t res) {
return _z80_sz_flags(res) |
(res & (Z80_YF|Z80_XF)) |
((res >> 8) & Z80_CF) |
((acc ^ val ^ res) & Z80_HF);
}
static inline uint8_t _z80_add_flags(uint8_t acc, uint8_t val, uint32_t res) {
return _z80_szyxch_flags(acc, val, res) | ((((val ^ acc ^ 0x80) & (val ^ res)) >> 5) & Z80_VF);
}
static inline uint8_t _z80_sub_flags(uint8_t acc, uint8_t val, uint32_t res) {
return Z80_NF | _z80_szyxch_flags(acc, val, res) | ((((val ^ acc) & (res ^ acc)) >> 5) & Z80_VF);
}
static inline uint8_t _z80_cp_flags(uint8_t acc, uint8_t val, uint32_t res) {
return Z80_NF |
_z80_sz_flags(res) |
(val & (Z80_YF|Z80_XF)) |
((res >> 8) & Z80_CF) |
((acc ^ val ^ res) & Z80_HF) |
((((val ^ acc) & (res ^ acc)) >> 5) & Z80_VF);
}
static inline uint8_t _z80_sziff2_flags(z80_t* cpu, uint8_t val) {
return (cpu->f & Z80_CF) | _z80_sz_flags(val) | (val & (Z80_YF|Z80_XF)) | (cpu->iff2 ? Z80_PF : 0);
}
static inline void _z80_add8(z80_t* cpu, uint8_t val) {
uint32_t res = cpu->a + val;
cpu->f = _z80_add_flags(cpu->a, val, res);
cpu->a = (uint8_t)res;
}
static inline void _z80_adc8(z80_t* cpu, uint8_t val) {
uint32_t res = cpu->a + val + (cpu->f & Z80_CF);
cpu->f = _z80_add_flags(cpu->a, val, res);
cpu->a = (uint8_t)res;
}
static inline void _z80_sub8(z80_t* cpu, uint8_t val) {
uint32_t res = (uint32_t) ((int)cpu->a - (int)val);
cpu->f = _z80_sub_flags(cpu->a, val, res);
cpu->a = (uint8_t)res;
}
static inline void _z80_sbc8(z80_t* cpu, uint8_t val) {
uint32_t res = (uint32_t) ((int)cpu->a - (int)val - (cpu->f & Z80_CF));
cpu->f = _z80_sub_flags(cpu->a, val, res);
cpu->a = (uint8_t)res;
}
static inline void _z80_and8(z80_t* cpu, uint8_t val) {
cpu->a &= val;
cpu->f = _z80_szp_flags[cpu->a] | Z80_HF;
}
static inline void _z80_xor8(z80_t* cpu, uint8_t val) {
cpu->a ^= val;
cpu->f = _z80_szp_flags[cpu->a];
}
static inline void _z80_or8(z80_t* cpu, uint8_t val) {
cpu->a |= val;
cpu->f = _z80_szp_flags[cpu->a];
}
static inline void _z80_cp8(z80_t* cpu, uint8_t val) {
uint32_t res = (uint32_t) ((int)cpu->a - (int)val);
cpu->f = _z80_cp_flags(cpu->a, val, res);
}
static inline void _z80_neg8(z80_t* cpu) {
uint32_t res = (uint32_t) (0 - (int)cpu->a);
cpu->f = _z80_sub_flags(0, cpu->a, res);
cpu->a = (uint8_t)res;
}
static inline uint8_t _z80_inc8(z80_t* cpu, uint8_t val) {
uint8_t res = val + 1;
uint8_t f = _z80_sz_flags(res) | (res & (Z80_XF|Z80_YF)) | ((res ^ val) & Z80_HF);
if (res == 0x80) {
f |= Z80_VF;
}
cpu->f = f | (cpu->f & Z80_CF);
return res;
}
static inline uint8_t _z80_dec8(z80_t* cpu, uint8_t val) {
uint8_t res = val - 1;
uint8_t f = Z80_NF | _z80_sz_flags(res) | (res & (Z80_XF|Z80_YF)) | ((res ^ val) & Z80_HF);
if (res == 0x7F) {
f |= Z80_VF;
}
cpu->f = f | (cpu->f & Z80_CF);
return res;
}
static inline void _z80_ex_de_hl(z80_t* cpu) {
uint16_t tmp = cpu->hl;
cpu->hl = cpu->de;
cpu->de = tmp;
}
static inline void _z80_ex_af_af2(z80_t* cpu) {
uint16_t tmp = cpu->af2;
cpu->af2 = cpu->af;
cpu->af = tmp;
}
static inline void _z80_exx(z80_t* cpu) {
uint16_t tmp;
tmp = cpu->bc; cpu->bc = cpu->bc2; cpu->bc2 = tmp;
tmp = cpu->de; cpu->de = cpu->de2; cpu->de2 = tmp;
tmp = cpu->hl; cpu->hl = cpu->hl2; cpu->hl2 = tmp;
}
static inline void _z80_rlca(z80_t* cpu) {
uint8_t res = (cpu->a << 1) | (cpu->a >> 7);
cpu->f = ((cpu->a >> 7) & Z80_CF) | (cpu->f & (Z80_SF|Z80_ZF|Z80_PF)) | (res & (Z80_YF|Z80_XF));
cpu->a = res;
}
static inline void _z80_rrca(z80_t* cpu) {
uint8_t res = (cpu->a >> 1) | (cpu->a << 7);
cpu->f = (cpu->a & Z80_CF) | (cpu->f & (Z80_SF|Z80_ZF|Z80_PF)) | (res & (Z80_YF|Z80_XF));
cpu->a = res;
}
static inline void _z80_rla(z80_t* cpu) {
uint8_t res = (cpu->a << 1) | (cpu->f & Z80_CF);
cpu->f = ((cpu->a >> 7) & Z80_CF) | (cpu->f & (Z80_SF|Z80_ZF|Z80_PF)) | (res & (Z80_YF|Z80_XF));
cpu->a = res;
}
static inline void _z80_rra(z80_t* cpu) {
uint8_t res = (cpu->a >> 1) | ((cpu->f & Z80_CF) << 7);
cpu->f = (cpu->a & Z80_CF) | (cpu->f & (Z80_SF|Z80_ZF|Z80_PF)) | (res & (Z80_YF|Z80_XF));
cpu->a = res;
}
static inline void _z80_daa(z80_t* cpu) {
uint8_t res = cpu->a;
if (cpu->f & Z80_NF) {
if (((cpu->a & 0xF)>0x9) || (cpu->f & Z80_HF)) {
res -= 0x06;
}
if ((cpu->a > 0x99) || (cpu->f & Z80_CF)) {
res -= 0x60;
}
}
else {
if (((cpu->a & 0xF)>0x9) || (cpu->f & Z80_HF)) {
res += 0x06;
}
if ((cpu->a > 0x99) || (cpu->f & Z80_CF)) {
res += 0x60;
}
}
cpu->f &= Z80_CF|Z80_NF;
cpu->f |= (cpu->a > 0x99) ? Z80_CF : 0;
cpu->f |= (cpu->a ^ res) & Z80_HF;
cpu->f |= _z80_szp_flags[res];
cpu->a = res;
}
static inline void _z80_cpl(z80_t* cpu) {
cpu->a ^= 0xFF;
cpu->f= (cpu->f & (Z80_SF|Z80_ZF|Z80_PF|Z80_CF)) |Z80_HF|Z80_NF| (cpu->a & (Z80_YF|Z80_XF));
}
static inline void _z80_scf(z80_t* cpu) {
cpu->f = (cpu->f & (Z80_SF|Z80_ZF|Z80_PF|Z80_CF)) | Z80_CF | (cpu->a & (Z80_YF|Z80_XF));
}
static inline void _z80_ccf(z80_t* cpu) {
cpu->f = ((cpu->f & (Z80_SF|Z80_ZF|Z80_PF|Z80_CF)) | ((cpu->f & Z80_CF)<<4) | (cpu->a & (Z80_YF|Z80_XF))) ^ Z80_CF;
}
static inline void _z80_add16(z80_t* cpu, uint16_t val) {
const uint16_t acc = cpu->hlx[cpu->hlx_idx].hl;
cpu->wz = acc + 1;
const uint32_t res = acc + val;
cpu->hlx[cpu->hlx_idx].hl = res;
cpu->f = (cpu->f & (Z80_SF|Z80_ZF|Z80_VF)) |
(((acc ^ res ^ val)>>8)&Z80_HF) |
((res >> 16) & Z80_CF) |
((res >> 8) & (Z80_YF|Z80_XF));
}
static inline void _z80_adc16(z80_t* cpu, uint16_t val) {
// NOTE: adc is ED-prefixed, so they are never rewired to IX/IY
const uint16_t acc = cpu->hl;
cpu->wz = acc + 1;
const uint32_t res = acc + val + (cpu->f & Z80_CF);
cpu->hl = res;
cpu->f = (((val ^ acc ^ 0x8000) & (val ^ res) & 0x8000) >> 13) |
(((acc ^ res ^ val) >>8 ) & Z80_HF) |
((res >> 16) & Z80_CF) |
((res >> 8) & (Z80_SF|Z80_YF|Z80_XF)) |
((res & 0xFFFF) ? 0 : Z80_ZF);
}
static inline void _z80_sbc16(z80_t* cpu, uint16_t val) {
// NOTE: sbc is ED-prefixed, so they are never rewired to IX/IY
const uint16_t acc = cpu->hl;
cpu->wz = acc + 1;
const uint32_t res = acc - val - (cpu->f & Z80_CF);
cpu->hl = res;
cpu->f = (Z80_NF | (((val ^ acc) & (acc ^ res) & 0x8000) >> 13)) |
(((acc ^ res ^ val) >> 8) & Z80_HF) |
((res >> 16) & Z80_CF) |
((res >> 8) & (Z80_SF|Z80_YF|Z80_XF)) |
((res & 0xFFFF) ? 0 : Z80_ZF);
}
static inline bool _z80_ldi_ldd(z80_t* cpu, uint8_t val) {
const uint8_t res = cpu->a + val;
cpu->bc -= 1;
cpu->f = (cpu->f & (Z80_SF|Z80_ZF|Z80_CF)) |
((res & 2) ? Z80_YF : 0) |
((res & 8) ? Z80_XF : 0) |
(cpu->bc ? Z80_VF : 0);
return cpu->bc != 0;
}
static inline bool _z80_cpi_cpd(z80_t* cpu, uint8_t val) {
uint32_t res = (uint32_t) ((int)cpu->a - (int)val);
cpu->bc -= 1;
uint8_t f = (cpu->f & Z80_CF)|Z80_NF|_z80_sz_flags(res);
if ((res & 0xF) > ((uint32_t)cpu->a & 0xF)) {
f |= Z80_HF;
res--;
}
if (res & 2) { f |= Z80_YF; }
if (res & 8) { f |= Z80_XF; }
if (cpu->bc) { f |= Z80_VF; }
cpu->f = f;
return (cpu->bc != 0) && !(f & Z80_ZF);
}
static inline bool _z80_ini_ind(z80_t* cpu, uint8_t val, uint8_t c) {
const uint8_t b = cpu->b;
uint8_t f = _z80_sz_flags(b) | (b & (Z80_XF|Z80_YF));
if (val & Z80_SF) { f |= Z80_NF; }
uint32_t t = (uint32_t)c + val;
if (t & 0x100) { f |= Z80_HF|Z80_CF; }
f |= _z80_szp_flags[((uint8_t)(t & 7)) ^ b] & Z80_PF;
cpu->f = f;
return (b != 0);
}
static inline bool _z80_outi_outd(z80_t* cpu, uint8_t val) {
const uint8_t b = cpu->b;
uint8_t f = _z80_sz_flags(b) | (b & (Z80_XF|Z80_YF));
if (val & Z80_SF) { f |= Z80_NF; }
uint32_t t = (uint32_t)cpu->l + val;
if (t & 0x0100) { f |= Z80_HF|Z80_CF; }
f |= _z80_szp_flags[((uint8_t)(t & 7)) ^ b] & Z80_PF;
cpu->f = f;
return (b != 0);
}
static inline uint8_t _z80_in(z80_t* cpu, uint8_t val) {
cpu->f = (cpu->f & Z80_CF) | _z80_szp_flags[val];
return val;
}
static inline uint8_t _z80_rrd(z80_t* cpu, uint8_t val) {
const uint8_t l = cpu->a & 0x0F;
cpu->a = (cpu->a & 0xF0) | (val & 0x0F);
val = (val >> 4) | (l << 4);
cpu->f = (cpu->f & Z80_CF) | _z80_szp_flags[cpu->a];
return val;
}
static inline uint8_t _z80_rld(z80_t* cpu, uint8_t val) {
const uint8_t l = cpu->a & 0x0F;
cpu->a = (cpu->a & 0xF0) | (val >> 4);
val = (val << 4) | l;
cpu->f = (cpu->f & Z80_CF) | _z80_szp_flags[cpu->a];
return val;
}
static inline uint8_t _z80_rlc(z80_t* cpu, uint8_t val) {
uint8_t res = (val<<1) | (val>>7);
cpu->f = _z80_szp_flags[res] | ((val>>7) & Z80_CF);
return res;
}
static inline uint8_t _z80_rrc(z80_t* cpu, uint8_t val) {
uint8_t res = (val>>1) | (val<<7);
cpu->f = _z80_szp_flags[res] | (val & Z80_CF);
return res;
}
static inline uint8_t _z80_rl(z80_t* cpu, uint8_t val) {
uint8_t res = (val<<1) | (cpu->f & Z80_CF);
cpu->f = _z80_szp_flags[res] | ((val>>7) & Z80_CF);
return res;
}
static inline uint8_t _z80_rr(z80_t* cpu, uint8_t val) {
uint8_t res = (val>>1) | ((cpu->f & Z80_CF)<<7);
cpu->f = _z80_szp_flags[res] | (val & Z80_CF);
return res;
}
static inline uint8_t _z80_sla(z80_t* cpu, uint8_t val) {
uint8_t res = val<<1;
cpu->f = _z80_szp_flags[res] | ((val>>7) & Z80_CF);
return res;
}
static inline uint8_t _z80_sra(z80_t* cpu, uint8_t val) {
uint8_t res = (val>>1) | (val & 0x80);
cpu->f = _z80_szp_flags[res] | (val & Z80_CF);
return res;
}
static inline uint8_t _z80_sll(z80_t* cpu, uint8_t val) {
uint8_t res = (val<<1) | 1;
cpu->f = _z80_szp_flags[res] | ((val>>7) & Z80_CF);
return res;
}
static inline uint8_t _z80_srl(z80_t* cpu, uint8_t val) {
uint8_t res = val>>1;
cpu->f = _z80_szp_flags[res] | (val & Z80_CF);
return res;
}
static inline uint64_t _z80_set_ab(uint64_t pins, uint16_t ab) {
return (pins & ~0xFFFF) | ab;
}
static inline uint64_t _z80_set_ab_x(uint64_t pins, uint16_t ab, uint64_t x) {
return (pins & ~0xFFFF) | ab | x;
}
static inline uint64_t _z80_set_ab_db(uint64_t pins, uint16_t ab, uint8_t db) {
return (pins & ~0xFFFFFF) | (db<<16) | ab;
}
static inline uint64_t _z80_set_ab_db_x(uint64_t pins, uint16_t ab, uint8_t db, uint64_t x) {
return (pins & ~0xFFFFFF) | (db<<16) | ab | x;
}
static inline uint8_t _z80_get_db(uint64_t pins) {
return (uint8_t)(pins>>16);
}
// CB-prefix block action
static inline bool _z80_cb_action(z80_t* cpu, uint8_t z0, uint8_t z1) {
const uint8_t x = cpu->opcode>>6;
const uint8_t y = (cpu->opcode>>3)&7;
uint8_t val, res;
switch (z0) {
case 0: val = cpu->b; break;
case 1: val = cpu->c; break;
case 2: val = cpu->d; break;
case 3: val = cpu->e; break;
case 4: val = cpu->h; break;
case 5: val = cpu->l; break;
case 6: val = cpu->dlatch; break; // (HL)
case 7: val = cpu->a; break;
default: _Z80_UNREACHABLE;
}
switch (x) {
case 0: // rot/shift
switch (y) {
case 0: res = _z80_rlc(cpu, val); break;
case 1: res = _z80_rrc(cpu, val); break;
case 2: res = _z80_rl(cpu, val); break;
case 3: res = _z80_rr(cpu, val); break;
case 4: res = _z80_sla(cpu, val); break;
case 5: res = _z80_sra(cpu, val); break;
case 6: res = _z80_sll(cpu, val); break;
case 7: res = _z80_srl(cpu, val); break;
default: _Z80_UNREACHABLE;
}
break;
case 1: // bit
res = val & (1<<y);
cpu->f = (cpu->f & Z80_CF) | Z80_HF | (res ? (res & Z80_SF) : (Z80_ZF|Z80_PF));
if (z0 == 6) {
cpu->f |= (cpu->wz >> 8) & (Z80_YF|Z80_XF);
}
else {
cpu->f |= val & (Z80_YF|Z80_XF);
}
break;
case 2: // res
res = val & ~(1 << y);
break;
case 3: // set
res = val | (1 << y);
break;
default: _Z80_UNREACHABLE;
}
// don't write result back for BIT
if (x != 1) {
cpu->dlatch = res;
switch (z1) {
case 0: cpu->b = res; break;
case 1: cpu->c = res; break;
case 2: cpu->d = res; break;
case 3: cpu->e = res; break;
case 4: cpu->h = res; break;
case 5: cpu->l = res; break;
case 6: break; // (HL)
case 7: cpu->a = res; break;
default: _Z80_UNREACHABLE;
}
return true;
}
else {
return false;
}
}
// compute the effective memory address for DD+CB/FD+CB instructions
static inline void _z80_ddfdcb_addr(z80_t* cpu, uint64_t pins) {
uint8_t d = _z80_get_db(pins);
cpu->addr = cpu->hlx[cpu->hlx_idx].hl + (int8_t)d;
cpu->wz = cpu->addr;
}
// special case opstate table slots
#define _Z80_OPSTATE_SLOT_CB (0)
#define _Z80_OPSTATE_SLOT_CBHL (1)
#define _Z80_OPSTATE_SLOT_DDFDCB (2)
#define _Z80_OPSTATE_SLOT_INT_IM0 (3)
#define _Z80_OPSTATE_SLOT_INT_IM1 (4)
#define _Z80_OPSTATE_SLOT_INT_IM2 (5)
#define _Z80_OPSTATE_SLOT_NMI (6)
#define _Z80_OPSTATE_NUM_SPECIAL_OPS (7)
#define _Z80_OPSTATE_STEP_INDIRECT (5) // see case-branch '6'
#define _Z80_OPSTATE_STEP_INDIRECT_IMM8 (13) // see case-branch '14'
static const uint16_t _z80_optable[256] = {
27, // 00: NOP (M:1 T:4 steps:1)
28, // 01: LD BC,nn (M:3 T:10 steps:7)
35, // 02: LD (BC),A (M:2 T:7 steps:4)
39, // 03: INC BC (M:2 T:6 steps:3)
42, // 04: INC B (M:1 T:4 steps:1)
43, // 05: DEC B (M:1 T:4 steps:1)
44, // 06: LD B,n (M:2 T:7 steps:4)
48, // 07: RLCA (M:1 T:4 steps:1)
49, // 08: EX AF,AF' (M:1 T:4 steps:1)
50, // 09: ADD HL,BC (M:2 T:11 steps:8)
58, // 0A: LD A,(BC) (M:2 T:7 steps:4)
62, // 0B: DEC BC (M:2 T:6 steps:3)
65, // 0C: INC C (M:1 T:4 steps:1)
66, // 0D: DEC C (M:1 T:4 steps:1)
67, // 0E: LD C,n (M:2 T:7 steps:4)
71, // 0F: RRCA (M:1 T:4 steps:1)
72, // 10: DJNZ d (M:4 T:13 steps:10)
82, // 11: LD DE,nn (M:3 T:10 steps:7)
89, // 12: LD (DE),A (M:2 T:7 steps:4)
93, // 13: INC DE (M:2 T:6 steps:3)
96, // 14: INC D (M:1 T:4 steps:1)
97, // 15: DEC D (M:1 T:4 steps:1)
98, // 16: LD D,n (M:2 T:7 steps:4)
102, // 17: RLA (M:1 T:4 steps:1)
103, // 18: JR d (M:3 T:12 steps:9)
112, // 19: ADD HL,DE (M:2 T:11 steps:8)
120, // 1A: LD A,(DE) (M:2 T:7 steps:4)
124, // 1B: DEC DE (M:2 T:6 steps:3)
127, // 1C: INC E (M:1 T:4 steps:1)
128, // 1D: DEC E (M:1 T:4 steps:1)
129, // 1E: LD E,n (M:2 T:7 steps:4)
133, // 1F: RRA (M:1 T:4 steps:1)
134, // 20: JR NZ,d (M:3 T:12 steps:9)
143, // 21: LD HL,nn (M:3 T:10 steps:7)
150, // 22: LD (nn),HL (M:5 T:16 steps:13)
163, // 23: INC HL (M:2 T:6 steps:3)
166, // 24: INC H (M:1 T:4 steps:1)
167, // 25: DEC H (M:1 T:4 steps:1)
168, // 26: LD H,n (M:2 T:7 steps:4)
172, // 27: DAA (M:1 T:4 steps:1)
173, // 28: JR Z,d (M:3 T:12 steps:9)
182, // 29: ADD HL,HL (M:2 T:11 steps:8)
190, // 2A: LD HL,(nn) (M:5 T:16 steps:13)
203, // 2B: DEC HL (M:2 T:6 steps:3)
206, // 2C: INC L (M:1 T:4 steps:1)
207, // 2D: DEC L (M:1 T:4 steps:1)
208, // 2E: LD L,n (M:2 T:7 steps:4)
212, // 2F: CPL (M:1 T:4 steps:1)
213, // 30: JR NC,d (M:3 T:12 steps:9)
222, // 31: LD SP,nn (M:3 T:10 steps:7)
229, // 32: LD (nn),A (M:4 T:13 steps:10)
239, // 33: INC SP (M:2 T:6 steps:3)
242, // 34: INC (HL) (M:3 T:11 steps:8)
250, // 35: DEC (HL) (M:3 T:11 steps:8)
258, // 36: LD (HL),n (M:3 T:10 steps:7)
265, // 37: SCF (M:1 T:4 steps:1)
266, // 38: JR C,d (M:3 T:12 steps:9)
275, // 39: ADD HL,SP (M:2 T:11 steps:8)
283, // 3A: LD A,(nn) (M:4 T:13 steps:10)
293, // 3B: DEC SP (M:2 T:6 steps:3)
296, // 3C: INC A (M:1 T:4 steps:1)
297, // 3D: DEC A (M:1 T:4 steps:1)
298, // 3E: LD A,n (M:2 T:7 steps:4)
302, // 3F: CCF (M:1 T:4 steps:1)
303, // 40: LD B,B (M:1 T:4 steps:1)
304, // 41: LD B,C (M:1 T:4 steps:1)
305, // 42: LD B,D (M:1 T:4 steps:1)
306, // 43: LD B,E (M:1 T:4 steps:1)
307, // 44: LD B,H (M:1 T:4 steps:1)
308, // 45: LD B,L (M:1 T:4 steps:1)
309, // 46: LD B,(HL) (M:2 T:7 steps:4)
313, // 47: LD B,A (M:1 T:4 steps:1)
314, // 48: LD C,B (M:1 T:4 steps:1)
315, // 49: LD C,C (M:1 T:4 steps:1)
316, // 4A: LD C,D (M:1 T:4 steps:1)
317, // 4B: LD C,E (M:1 T:4 steps:1)
318, // 4C: LD C,H (M:1 T:4 steps:1)
319, // 4D: LD C,L (M:1 T:4 steps:1)
320, // 4E: LD C,(HL) (M:2 T:7 steps:4)
324, // 4F: LD C,A (M:1 T:4 steps:1)
325, // 50: LD D,B (M:1 T:4 steps:1)
326, // 51: LD D,C (M:1 T:4 steps:1)
327, // 52: LD D,D (M:1 T:4 steps:1)
328, // 53: LD D,E (M:1 T:4 steps:1)
329, // 54: LD D,H (M:1 T:4 steps:1)
330, // 55: LD D,L (M:1 T:4 steps:1)
331, // 56: LD D,(HL) (M:2 T:7 steps:4)
335, // 57: LD D,A (M:1 T:4 steps:1)
336, // 58: LD E,B (M:1 T:4 steps:1)
337, // 59: LD E,C (M:1 T:4 steps:1)
338, // 5A: LD E,D (M:1 T:4 steps:1)
339, // 5B: LD E,E (M:1 T:4 steps:1)
340, // 5C: LD E,H (M:1 T:4 steps:1)
341, // 5D: LD E,L (M:1 T:4 steps:1)
342, // 5E: LD E,(HL) (M:2 T:7 steps:4)
346, // 5F: LD E,A (M:1 T:4 steps:1)
347, // 60: LD H,B (M:1 T:4 steps:1)
348, // 61: LD H,C (M:1 T:4 steps:1)
349, // 62: LD H,D (M:1 T:4 steps:1)
350, // 63: LD H,E (M:1 T:4 steps:1)
351, // 64: LD H,H (M:1 T:4 steps:1)