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aarch32.tex
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aarch32.tex
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%
% Copyright (C) 2014-2021 Anders Sonmark
%
% Copying and distribution of this file, with or without modification,
% are permitted in any medium without royalty provided the copyright
% notice and this notice are preserved. This file is offered as-is,
% without any warranty.
%
\documentclass{sheet}
\usepackage[utf8]{inputenc}
\usepackage[T1]{fontenc}
\usepackage{ae,aecompl}
\usepackage[english]{babel}
\usepackage[a4paper, landscape, margin=.1in]{geometry}
\usepackage{amssymb}
\usepackage{verbatim}
\usepackage{ulem}
\usepackage{makecell}
\def\sheetheaderfont{\bfseries}
\def\sheettablefont{\footnotesize\sffamily}
\def\sheetheadercolor{black!10}
\def\sheetrowcolor{black!5}
\newcolumntype{N}{>{\raggedleft\arraybackslash}m{1.7em}}
\def\tabcolsep{2pt}
\def\arraystretch{1.3}
\defsheet{asmtable}{4}{|m{4.6em} m{6.7em}|X|N|}
\defsheet{asmtable2}{4}{|m{6.5em} m{5.3em}|X|N|}
\defsheet{asmtable3}{4}{|m{5.0em} m{8.0em}|X|N|}
\defsheet{asmtable4}{4}{|m{5.1em} m{6.7em}|X|N|}
\defsheet{asmtable5}{4}{|m{7.5em} m{5.3em}|X|N|}
\defsheet{asmtable6}{4}{|m{6.0em} m{8.0em}|X|N|}
\defsheet{asmtable7}{4}{|m{5.8em} m{5.5em}|X|N|}
\defsheet{table-lX}{2}{|l X|}
\defsheet{table-lXN}{3}{|l|X|N|}
\defsheet{table-llX}{3}{|l l X|}
\defsheet{table-llXr}{4}{|l l X r|}
\pagefooter{ARM AArch32 version 11 page \thepage}
\begin{document}
\begin{multicols}{3}
\raggedcolumns
\begin{center}
{\Large\bfseries ARM AArch32 Quick Reference}
\end{center}
%
\begin{asmtable}{Load and Store Instructions}
LDMDA & rn\{!\}, rlist & rlist=[rn$-$4cnt$+$4]$^{ }_{32cnt}$; if(!) rn$-$=4cnt & A \\
LDMDB & rn\{!\}, rlist & rlist=[rn $-$ 4cnt]$^{ }_{32cnt}$; if(!) rn$-$=4cnt & \\
LDM\textit{IA} & rn\{!\}, rlist & rlist=[rn]$^{ }_{32cnt}$; if(!) rn $+$= 4cnt & \\
LDMIB & rn\{!\}, rlist & rlist=[rn $+$ 4]$^{ }_{32cnt}$; if(!) rn $+$= 4cnt & A \\
LDR\{T\} & rt, [addr] & rt = [addr]$^{ }_{32}$ & \\
LDRB\{T\} & rt, [addr] & rt = [addr]$^{\emptyset}_{8}$ & \\
LDRD & rt, rt2, [addr] & rt2:rt = [addr]$^{ }_{64}$ & \\
LDRH\{T\} & rt, [addr] & rt = [addr]$^{\emptyset}_{16}$ & \\
LDRSB\{T\} & rt, [addr] & rt = [addr]$^{\pm}_{8}$ & \\
LDRSH\{T\} & rt, [addr] & rt = [addr]$^{\pm}_{16}$ & \\
\textit{POP} & rlist & rlist = [SP]$^{ }_{32cnt}$; SP $+$= 4cnt & \\
\textit{PUSH} & rlist & SP $-$= 4cnt; [SP]$^{ }_{32cnt}$ = rlist & \\
STMDA & rn\{!\}, rlist & [rn$-$4cnt$+$4]$^{ }_{32cnt}$ = rlist; if(!) rn$-$=4cnt & A \\
STMDB & rn\{!\}, rlist & [rn $-$ 4cnt]$^{ }_{32cnt}$ = rlist; if(!) rn$-$=4cnt & \\
STM\textit{IA} & rn\{!\}, rlist & [rn]$^{ }_{32cnt}$ = rlist; if(!) rn $+$= 4cnt & \\
STMIB & rn\{!\}, rlist & [rn$+$4]$^{ }_{32cnt}$ = rlist; if(!) rn $+$= 4cnt & A \\
STR\{T\} & rt, [addr] & [addr]$^{ }_{32}$ = rt & \\
STRB\{T\} & rt, [addr] & [addr]$^{ }_{8}$ = rt$^{ }_{B0}$ & \\
STRD & rt, rt2, [addr] & [addr]$^{ }_{64}$ = rt2:rt & \\
STRH\{T\} & rt, [addr] & [addr]$^{ }_{16}$ = rt$^{ }_{H0}$ & \\
\end{asmtable}
%
\begin{table-llX}{ARM LDR/STR Addressing Modes}
non-T & [rn\{, \#$\pm$i$^{ }_{8}$\}]\{!\} & addr = rn $+$ i$^{\pm}_{ }$; if(!) rn = addr \\
xxR\{,B\} & [rn\{, \#$\pm$i$^{ }_{13}$\}]\{!\} & addr = rn $+$ i$^{\pm}_{ }$; if(!) rn = addr \\
any & [rn]\{, \#$\pm$i$^{ }_{8}$\} & addr = rn; rn $+$= i$^{\pm}_{ }$ \\
xxR\{,B\}\{T\} & [rn], \#$\pm$i$^{ }_{13}$ & addr = rn; rn $+$= i$^{\pm}_{ }$ \\
non-T & [rn, $\pm$rm]\{!\} & addr = rn $\pm$ rm; if(!) rn = addr \\
xxR\{,B\} & [rn, $\pm$rm\{, AS\}]\{!\} & addr = rn $\pm$ AS(rm); if(!) rn = addr \\
any & [rn], $\pm$rm & addr = rn; rn $\pm$= rm \\
xxR\{,B\}\{T\} & [rn], $\pm$rm\{, AS\} & addr = rn; rn $\pm$= AS(rm) \\
LD non-T & $\pm$rel$^{ }_{8}$ & addr = PC $+$ rel$^{\pm}_{ }$ \\
LDR\{,B\} & $\pm$rel$^{ }_{13}$ & addr = PC $+$ rel$^{\pm}_{ }$ \\
\end{table-llX}
%
\begin{table-llX}{Thumb2 LDR/STR Addressing Modes}
any & [rn\{, \#i$^{ }_{8}$\}] & addr = rn $+$ i$^{\emptyset}_{ }$ \\
xxR\{,B,H,SB,SH\} & [rn, \#i$^{ }_{12}$] & addr = rn $+$ i$^{\emptyset}_{ }$ \\
xxR\{,B,H,SB,SH\} & [rn, \#$\pm$i$^{ }_{8}$]\{!\} & addr = rn $+$ i$^{\pm}_{ }$; if(!) rn = addr \\
xxR\{,B,H,SB,SH\} & [rn], \#$\pm$i$^{ }_{8}$ & addr = rn; rn $+$= i$^{\pm}_{ }$ \\
xxR\{,B,H,SB,SH\} & [rn,rm\{, LSL \#i$^{ }_{2}$\}] & addr = rn $+$ rm $\lsl$ i \\
LDR\{,B,H,SB,SH\} & $\pm$rel$^{ }_{13}$ & addr = PC $+$ rel$^{\pm}_{ }$ \\
xxRD & [rn\{, \#$\pm$i$^{ }_{10}$\}]\{!\} & addr = rn $+$ i$^{\pm}_{9:2}$:0$^{ }_{2}$; if(!) rn=addr \\
xxRD & [rn], \#$\pm$i$^{ }_{10}$ & addr = rn; rn $+$= i$^{\pm}_{9:2}$:0$^{ }_{2}$ \\
LDRD & $\pm$rel$^{ }_{10}$ & addr = PC $+$ rel$^{\pm}_{9:2}$:0$^{ }_{2}$ \\
\end{table-llX}
%
\begin{asmtable}{Arithmetic Instructions}
ADC\{S\} & rd, rn, op2 & rd = rn $+$ op2 $+$ C & \\
ADD\{S\} & rd, rn, op2 & rd = rn $+$ op2 & \\
ADDW & rd, rn, \#i$^{ }_{12}$ & rd = rn $+$ i$^{\emptyset}_{ }$ & T \\
ADR & rd, $\pm$rel$^{ }_{12}$ & rd = PC $+$ rel$^{\pm}_{ }$ & \\
CMN & rn, op2 & rn $+$ op2 & \\
CMP & rn, op2 & rn $-$ op2 & \\
MLA & rd, rn, rm, ra & rd = ra $+$ rn $\umul$ rm & \\
MLA\{S\} & rd, rn, rm, ra & rd = ra $+$ rn $\umul$ rm & A \\
MLS & rd, rn, rm, ra & rd = ra $-$ rn $\umul$ rm & 6t \\
MUL & rd, rn, rm & rd = rn $\umul$ rm & \\
MUL\{S\} & rd, rn, rm & rd = rn $\umul$ rm & A \\
RSB\{S\} & rd, rn, op2 & rd = op2 $-$ rn & \\
RSC\{S\} & rd, rn, op2 & rd = op2 $-$ (rn $+$ C) & A \\
SBC\{S\} & rd, rn, op2 & rd = rn $-$ (op2 $+$ C) & \\
sDIV & rd, rn, rm & rd = rn $\udiv^{s}_{ }$ rm & 7 \\
sMLAL & rd, rd2, rn, rm & rd2:rd $+$= rn $\umul^{s}_{ }$ rm & \\
sMLAL\{S\} & rd, rd2, rn, rm & rd2:rd $+$= rn $\umul^{s}_{ }$ rm & A \\
sMULL & rd, rd2, rn, rm & rd2:rd = rn $\umul^{s}_{ }$ rm & \\
sMULL\{S\} & rd, rd2, rn, rm & rd2:rd = rn $\umul^{s}_{ }$ rm & A \\
sSAT & rd,\#i$^{ }_{5}$,rn\{, slr\} & rd = $\lfloor$rn $\lsl\asr$ sh$\rceil^{si}_{ }$ & 6 \\
SUB\{S\} & rd, rn, op2 & rd = rn $-$ op2 & \\
SUBW & rd, rn, \#i$^{ }_{12}$ & rd = rn $-$ i$^{\emptyset}_{ }$ & T \\
\end{asmtable}
%
\begin{asmtable}{Logical Instructions}
AND\{S\} & rd, rn, op2 & rd = rn \& op2 & \\
\textit{ASR\{S\}} & rd, rn, \#i$^{ }_{5}$ & rd = rn $\asr$ i & \\
\textit{ASR\{S\}} & rd, rn, rm & rd = rn $\asr$ rm & \\
BIC\{S\} & rd, rn, op2 & rd = rn \& $\sim$op2 & \\
EOR\{S\} & rd, rn, op2 & rd = rn $\oplus$ op2 & \\
\textit{LSL\{S\}} & rd, rn, \#i$^{ }_{5}$ & rd = rn $\lsl$ i & \\
\textit{LSL\{S\}} & rd, rn, rm & rd = rn $\lsl$ rm & \\
\textit{LSR\{S\}} & rd, rn, \#i$^{ }_{5}$ & rd = rn $\lsr$ i & \\
\textit{LSR\{S\}} & rd, rn, rm & rd = rn $\lsr$ rm & \\
MOV\{S\} & rd, op2 & rd = op2 & \\
MOVT & rd, \#i$^{ }_{16}$ & rd$^{ }_{H1}$ = i & 6t \\
MOVW & rd, \#i$^{ }_{16}$ & rd = i$^{\emptyset}_{ }$ & 6t \\
MVN\{S\} & rd, op2 & rd = $\sim$op2 & \\
ORN\{S\} & rd, rn, op2 & rd = rn | $\sim$op2 & T \\
ORR\{S\} & rd, rn, op2 & rd = rn | op2 & \\
\textit{ROR\{S\}} & rd, rn, \#i$^{ }_{5}$ & rd = rn $\ror$ i & \\
\textit{ROR\{S\}} & rd, rn, rm & rd = rn $\ror$ rm & \\
\textit{RRX\{S\}} & rd, rn & rd = C:rn$^{ }_{31:1}$; C = rn$^{ }_{0}$ & \\
TEQ & rn, op2 & rn $\oplus$ op2 & \\
TST & rn, op2 & rn \& op2 & \\
\end{asmtable}
%
\begin{asmtable}{Bit Manipulation Instructions}
BFC & rd, \#p, \#n & rd$^{ }_{p+n-1:p}$ = 0$^{ }_{n}$ & 6t \\
BFI & rd, rn, \#p, \#n & rd$^{ }_{p+n-1:p}$ = rn$^{ }_{n-1:0}$ & 6t \\
CLZ & rd, rn & rd = CountLeadingZeros(rn) & \\
\multicolumn{2}{|l|}{CRC32\{B,H,W\} rd, rn, rm} & rd = CRC32(rn, 0x04c11db7, rm$^{ }_{N0}$) & 8 \\
\multicolumn{2}{|l|}{CRC32C\{B,H,W\} rd, rn, rm} & rd = CRC32(rn, 0x1edc6f41, rm$^{ }_{N0}$) & 8 \\
RBIT & rd, rn & rd = ReverseBits(rn) & 6t \\
REV & rd, rn & rd = rn$^{ }_{B0}$:rn$^{ }_{B1}$:rn$^{ }_{B2}$:rn$^{ }_{B3}$ & 6 \\
REV16 & rd, rn & rd = rn$^{ }_{B2}$:rn$^{ }_{B3}$:rn$^{ }_{B0}$:rn$^{ }_{B1}$ & 6 \\
REVSH & rd, rn & rd = rn$^{\pm}_{B0}$:rn$^{ }_{B1}$ & 6 \\
sBFX & rd, rn, \#p, \#n & rd = rn$^{s}_{p+n-1:p}$ & 6t \\
sXTB & rd, rn\{, rb\} & rd = (rn $\ror$ sh)$^{s}_{B0}$ & 6 \\
sXTH & rd, rn\{, rb\} & rd = (rn $\ror$ sh)$^{s}_{H0}$ & 6 \\
\end{asmtable}
%
\begin{asmtable}{Branch and Jump Instructions}
B & rel$^{ }_{26}$ & PC = PC $+$ rel$^{\pm}_{25:2}$:0$^{ }_{2}$ & A \\
B & rel$^{ }_{25}$ & PC = PC $+$ rel$^{\pm}_{24:1}$:0$^{ }_{1}$ & T \\
Bcc & rel$^{ }_{21}$ & if(cc) PC = PC $+$ rel$^{\pm}_{20:1}$:0$^{ }_{1}$ & I \\
BKPT & \#i$^{ }_{16}$ & BreakPoint(i) & I \\
BL & rel$^{ }_{26}$ & LR=PC$^{ }_{31:1}$:0$^{ }_{1}$; PC $+$= rel$^{\pm}_{25:2}$:0$^{ }_{2}$ & A \\
BL & rel$^{ }_{25}$ & LR=PC$^{ }_{31:1}$:1$^{ }_{1}$; PC $+$= rel$^{\pm}_{24:1}$:0$^{ }_{1}$ & T \\
BLX & rel$^{ }_{26}$ & LR=PC$^{ }_{31:1}$:0$^{ }_{1}$; Set=1; PC$+$=rel$^{\pm}_{25:1}$:0$^{ }_{1}$ & A \\
BLX & rel$^{ }_{25}$ & LR=PC$^{ }_{31:1}$:1$^{ }_{1}$; Set=0; PC$+$=rel$^{\pm}_{24:2}$:0$^{ }_{2}$ & T \\
BLX & rn & LR=PC$^{ }_{31:1}$:0$^{ }_{1}$; Set=rn$^{ }_{0}$; PC=rn$^{ }_{31:1}$:0$^{ }_{1}$ & \\
BX & rn & Set = rn$^{ }_{0}$; PC = rn$^{ }_{31:1}$:0$^{ }_{1}$ & \\
%BXJ & rn & Set = 2; PC = rn$^{ }_{31:1}$:0 & \\
CBNZ & rn, rel$^{ }_{7}$ & if(rn $\ne$ 0) PC $+$= rel$^{\emptyset}_{6:1}$:0$^{ }_{1}$ & I,T \\
CBZ & rn, rel$^{ }_{7}$ & if(rn $\eq$ 0) PC $+$= rel$^{\emptyset}_{6:1}$:0$^{ }_{1}$ & I,T \\
TBB & [rn, rm] & PC = PC $+$ 2 $\umul$ [rn $+$ rm]$^{\emptyset}_{8}$ & T \\
TBH & [rn,rm, LSL \#1] & PC = PC $+$ 2 $\umul$ [rn $+$ 2 $\umul$ rm]$^{\emptyset}_{16}$ & T \\
\end{asmtable}
%
\begin{table-lXN}{Operand 2 (op2)}
\#i$^{ }_{32}$ & i$^{ }_{8}$ $\ror$ i$^{ }_{4}$:0$^{ }_{1}$ & A \\
\#i$^{ }_{32}$ & 0$^{ }_{24}$:i$^{ }_{8}$, 0$^{ }_{8}$:i$^{ }_{8}$0$^{ }_{8}$:i$^{ }_{8}$, i$^{ }_{8}$:0$^{ }_{8}$i$^{ }_{8}$:0$^{ }_{8}$, or i$^{ }_{8}$:i$^{ }_{8}$i$^{ }_{8}$:i$^{ }_{8}$ & T \\
\#i$^{ }_{32}$ & 1$^{ }_{1}$:i$^{ }_{7}$ $\lsl$ \{1..24\} & T \\
rm & rm & \\
rm, LSL \#n & rm $\lsl$ \{1..31\} & \\
rm, LSR \#n & rm $\lsr$ \{1..32\} & \\
rm, ASR \#n & rm $\asr$ \{1..32\} & \\
rm, ROR \#n & rm $\ror$ \{1..31\} & \\
rm, RRX & C:rm$^{ }_{31:1}$; C = rm$^{ }_{0}$ & \\
rm, LSL rs & rm $\lsl$ rs & A \\
rm, LSR rs & rm $\lsr$ rs & A \\
rm, ASR rs & rm $\asr$ rs & A \\
rm, ROR rs & rm $\ror$ rs & A \\
\end{table-lXN}
%
\begin{asmtable}{DSP Extended Arithmetic Instructions}
QADD & rd, rn, rm & rd = $\lfloor$rn $+$ rm$\rceil^{S32}$ & D \\
QDADD & rd, rn, rm & rd = $\lfloor$rn $+$ $\lfloor$2 $\umul$ rm$\rceil^{S32}$ $\rceil^{S32}$ & D \\
QDSUB & rd, rn, rm & rd = $\lfloor$rn $-$ $\lfloor$2 $\umul$ rm$\rceil^{S32}$ $\rceil^{S32}$ & D \\
QSUB & rd, rn, rm & rd = $\lfloor$rn $-$ rm$\rceil^{S32}$ & D \\
SMLAxy & rd, rn, rm, ra & rd = ra $+$ rn$^{\pm}_{Hx}$ $\smul$ rm$^{\pm}_{Hy}$ & D \\
SMLaD & rd, rn, rm, ra & rd = ra $+$ rn$^{\pm}_{H0}$$\smul$rm$^{\pm}_{H0}$ $\pm$ rn$^{\pm}_{H1}$$\smul$rm$^{\pm}_{H1}$ & 6,D \\
SMLaDX & rd, rn, rm, ra & rd = ra $+$ rn$^{\pm}_{H0}$$\smul$rm$^{\pm}_{H1}$ $\pm$ rn$^{\pm}_{H1}$$\smul$rm$^{\pm}_{H0}$ & D \\
SMLaLD & rd, rd2, rn, rm & rd2:rd $+$= rn$^{\pm}_{H0}$$\smul$rm$^{\pm}_{H0}$ $\pm$ rn$^{\pm}_{H1}$$\smul$rm$^{\pm}_{H1}$ & 6,D \\
SMLaLDX & rd, rd2, rn, rm & rd2:rd $+$= rn$^{\pm}_{H0}$$\smul$rm$^{\pm}_{H1}$ $\pm$ rn$^{\pm}_{H1}$$\smul$rm$^{\pm}_{H0}$ & D \\
SMLALxy & rd, rd2, rn, rm & rd2:rd $+$= rn$^{\pm}_{Hx}$ $\smul$ rm$^{\pm}_{Hy}$ & D \\
SMLAWy & rd, rn, rm, ra & rd = ra $+$ rn $\smul$ rm$^{\pm}_{Hy}$ & D \\
SMMLa & rd, rn, rm, ra & rd = ra $\pm$ ((rn $\smul$ rm) $\asr$ 32) & 6,D \\
SMMLaR & rd, rn, rm, ra & rd = ra $\pm$ ((rn $\smul$ rm) $\asr^{R}_{ }$ 32) & D \\
SMMUL & rd, rn, rm & rd = (rn $\smul$ rm) $\asr$ 32 & 6,D \\
SMMULR & rd, rn, rm & rd = (rn $\smul$ rm) $\asr^{R}_{ }$ 32 & D \\
SMUaD & rd, rn, rm & rd = rn$^{\pm}_{H0}$ $\smul$ rm$^{\pm}_{H0}$ $\pm$ rn$^{\pm}_{H1}$ $\smul$ rm$^{\pm}_{H1}$ & 6,D \\
SMUaDX & rd, rn, rm & rd = rn$^{\pm}_{H0}$ $\smul$ rm$^{\pm}_{H1}$ $\pm$ rn$^{\pm}_{H1}$ $\smul$ rm$^{\pm}_{H0}$ & D \\
SMULxy & rd, rn, rm & rd = rn$^{\pm}_{Hx}$ $\smul$ rm$^{\pm}_{Hy}$ & D \\
SMULWy & rd, rn, rm & rd = (rn $\smul$ rm$^{\pm}_{Hy}$) $\asr$ 16 & D \\
SSAT16 & rd, \#i$^{ }_{4}$, rn & rd = $\lfloor$rn$^{\pm}_{H1}$$\rceil^{Si \pm}_{ }$:$\lfloor$rn$^{\pm}_{H0}$$\rceil^{Si \pm}_{ }$ & 6,D \\
UMAAL & rd, rd2, rn, rm & rd2:rd = rd2 $+$ rd $+$ rn $\umul$ rm & D \\
USAD8 & rd, rn, rm & rd = $\sum_{n=0}^{3}$($\lvert$rn$^{\emptyset}_{Bn}$ $-$ rm$^{\emptyset}_{Bn}$$\rvert$) & 6,D \\
USADA8 & rd, rn, rm, ra & rd = ra $+$ $\sum_{n=0}^{3}$($\lvert$rn$^{\emptyset}_{Bn}$ $-$ rm$^{\emptyset}_{Bn}$$\rvert$) & 6,D \\
USAT16 & rd, \#i$^{ }_{4}$, rn & rd = $\lfloor$rn$^{\pm}_{H1}$$\rceil^{Ui \emptyset}_{ }$:$\lfloor$rn$^{\pm}_{H0}$$\rceil^{Ui \emptyset}_{ }$ & 6,D \\
\end{asmtable}
%
\begin{asmtable}{Parallel Instructions}
pADD16 & rd, rn, rm & rd$^{ }_{H*}$ = p(rn$^{ }_{H*}$ $+$ rm$^{ }_{H*}$) & 6,D \\
pADD8 & rd, rn, rm & rd$^{ }_{B*}$ = p(rn$^{ }_{B*}$ $+$ rm$^{ }_{B*}$) & 6,D \\
pASX & rd, rn, rm & rd = p(rn$^{ }_{H1}$ $+$ rm$^{ }_{H0}$):p(rn$^{ }_{H0}$ $-$ rm$^{ }_{H1}$) & 6,D \\
pSAX & rd, rn, rm & rd = p(rn$^{ }_{H1}$ $-$ rm$^{ }_{H0}$):p(rn$^{ }_{H0}$ $+$ rm$^{ }_{H1}$) & 6,D \\
pSUB16 & rd, rn, rm & rd$^{ }_{H*}$ = p(rn$^{ }_{H*}$ $-$ rm$^{ }_{H*}$) & 6,D \\
pSUB8 & rd, rn, rm & rd$^{ }_{B*}$ = p(rn$^{ }_{B*}$ $-$ rm$^{ }_{B*}$) & 6,D \\
SEL & rd, rn, rm & rd$^{ }_{B*}$ = GE* ? rn$^{ }_{B*}$ : rm$^{ }_{B*}$ & 6,D \\
\end{asmtable}
%
\begin{table-lX}{Parallel Instruction Prefixes (p)}
Q & Signed operation, Results are saturated \\
S & Signed operation, Results are truncated \\
SH & Signed operation, Results are right shifted by one \\
U & Unsigned operation, Results are truncated \\
UH & Unsigned operation, Results are right shifted by one \\
UQ & Unsigned operation, Results are saturated \\
\end{table-lX}
%
\begin{asmtable}{Packing and Unpacking Instructions}
PKHBT & rd, rn, rm\{, sl\} & rd = (rm $\lsl$ sh)$^{ }_{H1}$:rn$^{ }_{H0}$ & 6,D \\
PKHTB & rd, rn, rm\{, sr\} & rd = rn$^{ }_{H1}$:(rm $\asr$ sh)$^{ }_{H0}$ & 6,D \\
SXTAB & rd, rn, rm\{, rb\} & rd = rn $+$ (rm $\ror$ sh)$^{\pm}_{B0}$ & 6,D \\
SXTAB16 & rd, rn, rm\{, rb\} & rd$^{ }_{H*}$ = rn$^{ }_{H*}$ $+$ (rm $\ror$ sh)$^{\pm}_{B2*}$ & 6,D \\
SXTAH & rd, rn, rm\{, rb\} & rd = rn $+$ (rm $\ror$ sh)$^{\pm}_{H0}$ & 6,D \\
SXTB16 & rd, rn\{, rb\} & rd$^{ }_{H*}$ = (rn $\ror$ sh)$^{\pm}_{B2*}$ & 6,D \\
UXTAB & rd, rn, rm\{, rb\} & rd = rn $+$ (rm $\ror$ sh)$^{\emptyset}_{B0}$ & 6,D \\
UXTAB16 & rd, rn, rm\{, rb\} & rd$^{ }_{H*}$ = rn$^{ }_{H*}$ $+$ (rm$ \ror$ sh)$^{\emptyset}_{B2*}$ & 6,D \\
UXTAH & rd, rn, rm\{, rb\} & rd = rn $+$ (rm $\ror$ sh)$^{\emptyset}_{H0}$ & 6,D \\
UXTB16 & rd, rn\{, rb\} & rd$^{ }_{H*}$ = (rn $\ror$ sh)$^{\emptyset}_{B2*}$ & 6,D \\
\end{asmtable}
%
\begin{asmtable}{Exclusive Load and Store Instructions}
CLREX & & ClearExclusiveLocal() & 6k,I \\
LDREX & rt, [rn] & rt = [rn]$^{ }_{32}$; SetExclusiveMonitor & 6k \\
LDREX & rt, [rn, \#i$^{ }_{10}$] & rt = [rn$+$i$^{\emptyset}_{9:2}$:0$^{ }_{2}$]$^{ }_{32}$; SetExclusiveMonitor & 6k,T \\
LDREXB & rt, [rn] & rt = [rn]$^{\emptyset}_{8}$; SetExclusiveMonitor & 6k \\
LDREXD & rt, rt2, [rm] & rt2:rt = [rm]$^{ }_{64}$; SetExclusiveMonitor & 6k \\
LDREXH & rt, [rn] & rt = [rn]$^{\emptyset}_{16}$; SetExclusiveMonitor & 6k \\
STREX & rd, rt, [rn] & if(Pass) [rn]$^{ }_{32}$ = rt; rd = Pass ? 1 : 0 & 6k \\
STREX & rd, rt, [rn,\#i$^{ }_{10}$] & if(Pass) [rn$+$i$^{\emptyset}_{9:2}$:0$^{ }_{2}$]$^{ }_{32}$=rt; rd=Pass?1:0 & 6k,T \\
STREXB & rd, rt, [rn] & if(Pass) [rn]$^{ }_{8}$ = rt$^{ }_{B0}$; rd = Pass?1:0 & 6k \\
STREXD & rd, rt, rt2, [rn] & if(Pass) [rn]$^{ }_{64}$ = rt2:rt; rd = Pass?1:0 & 6k \\
STREXH & rd, rt, [rn] & if(Pass) [rn]$^{ }_{16}$ = rt$^{ }_{H0}$; rd = Pass?1:0 & 6k \\
\end{asmtable}
%
\begin{asmtable}{System Instructions}
CPS & \#mode & MODE = mode & 6 \\
CPSI\{D,E\} & \{aif\}\{, \#mode\} & \{a\}\{i\}\{f\} = (E ? 1 : 0); MODE = mode & 6 \\
%DCPS\{123\} & \{\#i$^{ }_{16}$\} & DebugChangePE\{123\}(i) & 8,T \\
ERET & & PC = LR; CPSR = SPSR & 7 \\
%HLT & \#i$^{ }_{16}$ & DebugHalt(i) & 8 \\
HVC & \#i$^{ }_{16}$ & CallHypervisor(i) & 7 \\
MRS & rd, xPSR & rd = \{CPSR,SPSR\} & \\
MRS & rd, Rbanked & rd = Rbanked & 7 \\
MSR & xPSR, rn & \{CPSR,SPSR\} = rn & \\
MSR & Rbanked, rn & Rbanked = rn & 7 \\
MSR & xPSR\_\{cxsf\},\#i & \{CPSR,SPSR\}$^{ }_{f,s,x,c}$ = i$^{ }_{f,s,x,c}$ & A \\
MSR & xPSR\_\{cxsf\}, rn & \{CPSR,SPSR\}$^{ }_{f,s,x,c}$ = rn$^{ }_{f,s,x,c}$ & \\
RFEdi & rn\{!\} & LDMdi rn\{!\}, \{PC, CPSR\} & \\
SETPAN & \#i$^{ }_{1}$ & PSTATE.PAN = i & 8{\tiny 1},I \\
SMC & \#i$^{ }_{4}$ & CallSecureMonitor(i) & 6k,A \\
SRSdi & SP\{!\}, \#mode & STMdi SP\_mode\{!\}, \{LR, SPSR\} & 6 \\
SVC & \#i$^{ }_{24}$ & CallSupervisor(i) & A \\
\end{asmtable}
%
\begin{asmtable}{Special Instructions}
DBG & \#i$^{ }_{4}$ & DebugHint(i) & 7 \\
%DFB & & DataFullBarrier() & 8,R \\
DMB & option & DataMemornBarrier(option) & 7,I \\
DSB & option & DataSynchronizationBarrier(option) & 7,I \\
ESB & & ErrorSyncBarrier() & 8{\tiny 2},I \\
ISB & SY & InstructionSynchronizationBarrier(SY) & 7,I \\
NOP & & & 6k \\
PLD\{W\} & [addr] & PreloadData(addr) & \\
%PLD\{W\} & [rd, \#i$^{ }_{12}$] & PreloadData(rd $+$ i) & \\
%PLD\{W\} & [rd, \#$-$i$^{ }_{8}$] & PreloadData(rd $-$ i) & \\
%PLD\{W\} & [rd, \#$-$i$^{ }_{12}$] & PreloadData(rd $-$ i) & A \\
%PLD & $\pm$rel$^{ }_{12}$ & PreloadData(PC $\pm$ rel) & \\
%PLD\{W\} & [rd, rn\{, LSL \#i$^{ }_{2}$\}] & PreloadData(rd $+$ rn $\lsl$ i) & \\
%PLD\{W\} & [rd, $\pm$rn\{, AS\}] & PreloadData(rd $\pm$ AS(rn)) & A \\
PLI & [addr] & PreloadInstr(addr) & 7 \\
%PLI & [rd, \#i$^{ }_{12}$] & PreloadInstr(rd $+$ i) & 7 \\
%PLI & [rd, \#$-$i$^{ }_{8}$] & PreloadInstr(rd $-$ i) & 7 \\
%PLI & [rd, \#$-$i$^{ }_{12}$] & PreloadInstr(rd $-$ i) & 7,A \\
%PLI & $\pm$rel$^{ }_{12}$ & PreloadInstr(PC $\pm$ rel) & 7\\
%PLI & [rd, rn\{, LSL \#i$^{ }_{2}$\}] & PreloadInstr(rd $+$ rn $\lsl$ i) & 7 \\
%PLI & [rd, $\pm$rn\{, AS\}] & PreloadInstr(rd $\pm$ AS(rn)) & A,7 \\
SETEND & \{BE,LE\} & EndianState = \{BE,LE\} & 6,I \\
SEV & & SendEvent() & 6k \\
SEVL & & EventRegisterSet() & 8 \\
UDF & \#i$^{ }_{16}$ & UndefinedException(i) & \\
WFE & & WaitForEvent() & 6k \\
WFI & & WaitForInterrupt() & 6k \\
YIELD & & HintYield() & 6k \\
\end{asmtable}
%
\begin{table-lX}{Keys}
\{S\} & Optional suffix, if present update flags \\
\{t\} & Conditional for additional instructions (T or E) \\
\{T\} & LDR/STR instruction uses user privileges \\
a & A to add or S to subtract \\
x, y & Selects bottom (B) or top (T) half of register(s) \\
di & DA, DB, IA or IB for decrease/increase before/after \\
i & Immediate operand, range 0..max / 1..max+1 \\
s & Operation signess (S or U) \\
rd, rn, rm, ra & General register \\
Rbanked & Banked register (R\{8,9,10,11,12\}\_\{usr,fiq\}, \{SP,LR\}\_usr, \newline \{SP,LR,SPSR\}\_\{fiq,irq,svc,abt,und,mon,hyp\}) \\
rlist & Comma separated list of registers within \{ \} \\
xPSR & APSR, CPSR or SPSR \\
B\{0,1,2,3\} & Selected byte (bits 7:0, 15:8, 23:16 or 31:24) \\
H\{0,1\} & Selected half word (bits 15:0 or 31:16) \\
\{, rb\} & Optional rotate (ROR 8, ROR 16 or ROR 24) \\
\{, slr\} & Optional shift (LSL \#\{1..31\} or ASR \#\{1..32\}) \\
\{, sl\} & Optional left shift (LSL \#\{1..31\}) \\
\{, sr\} & Optional right shift (ASR \#\{1..32\}) \\
\{, AS\} & Optional ARM shift or rotate (LSL/ROR \#\{1..31\}, LSR/ASR \#\{1..32\}, or RRX) \\
value$^{\pm}_{ }$, value$^{\emptyset}_{ }$ & Value is sign/zero extended\\
$\smul$ $\sdiv$ $\asr$ & Operation is signed \\
$\lsr^{R}_{ }$ $\asr^{R}_{ }$ & Shift result is rounded instead of truncated \\
$\lfloor$x$\rceil^{sz}$ & Value is saturated to z bits of type s \\
$\lvert$x$\rvert$ & Absolute of value \\
\end{table-lX}
%
\begin{table-llX}{General Registers}
R0-R3 & & Arguments and return values (usable by Thumb16) \\
R4-R7 & & General purpose (must be preserved, usable by Thumb16) \\
R8-R9 & & General purpose (must be preserved) \\
R10 & SL & Stack Limit (must be preserved) \\
R11 & FP & Frame Pointer (must be preserved) \\
R12 & IP & Intra-procedure-call scratch \\
R13 & SP & Stack pointer \\
R14 & LR & Return address \\
R15 & PC & Program counter \\
\end{table-llX}
%
\begin{table-llX}{Condition Codes (cc)}
EQ & Equal & Z \\
NE & Not equal & !Z \\
CS/HS & Carry set, Unsigned higher or same & C \\
CC/LO & Carry clear, Unsigned lower & !C \\
MI & Minus, Negative & N \\
PL & Plus, Positive or zero & !N \\
VS & Overflow & V \\
VC & No overflow & !V \\
HI & Unsigned higher & C \& !Z \\
LS & Unsigned lower or same & !C | Z \\
GE & Signed greater than or equal & N $=$ V \\
LT & Signed less than & N $\ne$ V \\
GT & Signed greater than & !Z \& N $=$ V \\
LE & Signed less than or equal & Z | N $\ne$ V \\
AL & Always (default) & 1 \\
\end{table-llX}
%
\begin{table-lX}{DMB and DSB Options}
SY & Full system, Read and write \\
\{SY\}ST & Full system, Write only \\
ISH & Inner shareable, Read and write \\
ISHST & Inner shareable, Write only \\
NSH & Non-shareable, Read and write \\
NSHST & Non-shareable, Write only \\
OSH & Outer shareable, Read and write \\
OSHST & Outer sharable, Write only \\
\end{table-lX}
%
\begin{table-lX}{Notes for Instruction Set}
6,6k,6t,7 & Introduced in ARMv6, ARMv6k, ARMv6T2, or ARMv7 \\
8,8{\tiny 1},8{\tiny 2} & Introduced in ARMv8, ARMv8.1, or ARMv8.2 \\
A & Only available in ARM mode \\
D & Not available on ARM-M without DSP extension \\
H & Thumb16 instruction can use high registers \\
I & Can't be conditional \\
S & Thumb16 instruction must have S suffix unless in IT block \\
T & Only available in Thumb mode \\
\end{table-lX}
%
\begin{asmtable}{Thumb16 Bitwise and Move Instructions}
AND\{S\} & rd, rn & rd = rd \& rn & S \\
ASR\{S\} & rd, rn, \#i$^{ }_{5}$ & rd = rn $\asr$ i & S \\
ASR\{S\} & rd, rn & rd = rd $\asr$ rn & S \\
BIC\{S\} & rd, rn & rd = rd \& $\sim$rn & S \\
EOR\{S\} & rd, rn & rd = rd $\oplus$ rn & S \\
LSL\{S\} & rd, rn, \#i$^{ }_{5}$ & rd = rn $\lsl$ i & S \\
LSL\{S\} & rd, rn & rd = rd $\lsl$ rn & S \\
LSR\{S\} & rd, rn, \#i$^{ }_{5}$ & rd = rn $\lsr$ i & S \\
LSR\{S\} & rd, rn & rd = rd $\lsr$ rn & S \\
MOV & rd, rn & rd = rn & H \\
MOVS & rd, rn & rd = rn & \\
MOV\{S\} & rd, \#i$^{ }_{8}$ & rd = i$^{\emptyset}_{ }$ & S \\
MVN\{S\} & rd, rn & rd = $\sim$rn & S \\
ORR\{S\} & rd, rn & rd = rd | rn & S \\
REV & rd, rn & rd = rn$^{ }_{B0}$:rn$^{ }_{B1}$:rn$^{ }_{B2}$:rn$^{ }_{B3}$ & 6 \\
REV16 & rd, rn & rd = rn$^{ }_{B2}$:rn$^{ }_{B3}$:rn$^{ }_{B0}$:rn$^{ }_{B1}$ & 6 \\
REVSH & rd, rn & rd = rn$^{\pm}_{B0}$:rn$^{ }_{B1}$ & 6 \\
ROR\{S\} & rd, rn & rd = rd $\ror$ rn & S \\
SXTB & rd, rn & rd = rn$^{\pm}_{B0}$ & \\
SXTH & rd, rn & rd = rn$^{\pm}_{H0}$ & \\
TST & rn, rm & rn \& rm & \\
UXTB & rd, rn & rd = rn$^{\emptyset}_{B0}$ & 6 \\
UXTH & rd, rn & rd = rn$^{\emptyset}_{H0}$ & 6 \\
\end{asmtable}
%
\begin{asmtable}{Thumb16 Branch and Special Instructions}
B & rel$^{ }_{12}$ & PC = PC $+$ rel$^{\pm}_{11:1}$:0$^{ }_{1}$ & \\
Bcc & rel$^{ }_{9}$ & if(cc) PC = PC $+$ rel$^{\pm}_{8:1}$:0$^{ }_{1}$ & I \\
BKPT & \#i$^{ }_{8}$ & BreakPoint(i$^{\emptyset}_{ }$) & I \\
BL & rel$^{ }_{25}$ & LR=PC$^{ }_{31:1}$:1$^{ }_{1}$; PC $+$= rel$^{\pm}_{24:1}$:0$^{ }_{1}$ & \\
BLX & rel$^{ }_{25}$ & LR=PC$^{ }_{31:1}$:1$^{ }_{1}$; Set=0; PC$+$=rel$^{\pm}_{24:2}$:0$^{ }_{2}$ & \\
BLX & rn & LR=PC$^{ }_{31:1}$:1$^{ }_{1}$; Set=rn$^{ }_{0}$; PC=rn$^{ }_{31:1}$:0$^{ }_{1}$ & \\
BX & rn & Set = rn$^{ }_{0}$; PC = rn$^{ }_{31:1}$:0$^{ }_{1}$ & \\
CBNZ & rn, rel$^{ }_{7}$ & if(rn $\ne$ 0) PC $+$= rel$^{\emptyset}_{6:1}$:0$^{ }_{1}$ & I,T \\
CBZ & rn, rel$^{ }_{7}$ & if(rn $\eq$ 0) PC $+$= rel$^{\emptyset}_{6:1}$:0$^{ }_{1}$ & I,T \\
CPSI\{D,E\} & \{aif\} & \{a\}\{i\}\{f\} = (E ? 1 : 0) & 6 \\
%HLT & \#i$^{ }_{6}$ & DebugHalt(i) & 8 \\
IT\{t\{t\{t\}\}\} & cc & if(cc) NextInstruction & 6t,I \\
NOP & & & 6k \\
SETEND & \{BE,LE\} & EndianState = \{BE,LE\} & 6,I \\
SETPAN & \#i$^{ }_{1}$ & PSTATE.PAN = i & 8{\tiny 1},I \\
SEV & & SendEvent() & 7 \\
SEVL & & EventRegisterSet() & 8 \\
SVC & \#i$^{ }_{8}$ & CallSupervisor(i) & \\
UDF & \#i$^{ }_{8}$ & UndefinedException(i) & \\
WFE & & WaitForEvent() & 7 \\
WFI & & WaitForInterrupt() & 7 \\
YIELD & & HintYield() & 7 \\
\end{asmtable}
%
\begin{asmtable}{Thumb16 Arithmetic Instructions}
ADC\{S\} & rd, rn & rd = rd $+$ rn $+$ C & S \\
ADD\{S\} & rd, rn, \#i$^{ }_{3}$ & rd = rn $+$ i$^{\emptyset}_{ }$ & S \\
ADD\{S\} & rd, \#i$^{ }_{8}$ & rd = rd $+$ i$^{\emptyset}_{ }$ & S \\
ADD\{S\} & rd, rn, rm & rd = rn $+$ rm & S \\
ADD & rd, rn & rd = rd $+$ rn & H \\
ADD & rd, SP, \#i$^{ }_{10}$ & rd = SP $+$ i$^{\emptyset}_{9:2}$:0$^{ }_{2}$ & \\
ADD & SP, \#i$^{ }_{9}$ & SP = SP $+$ i$^{\emptyset}_{8:2}$:0$^{ }_{2}$ & \\
ADR & rd, rel$^{ }_{10}$ & rd = PC $+$ rel$^{\emptyset}_{9:2}$:0$^{ }_{2}$ & \\
CMN & rn, rm & rn $+$ rm & \\
CMP & rn, \#i$^{ }_{8}$ & rn $-$ i$^{\emptyset}_{ }$ & \\
CMP & rn, rm & rn $-$ rm & H \\
MUL\{S\} & rd, rn & rd = rd $\umul$ rn & S \\
RSB\{S\} & rd, rn, \#0 & rd = 0 $-$ rn & S \\
SBC\{S\} & rd, rn & rd = rd $-$ (rn $+$ C) & S \\
SUB\{S\} & rd, rn, \#i$^{ }_{3}$ & rd = rn $-$ i$^{\emptyset}_{ }$ & S \\
SUB\{S\} & rd, \#i$^{ }_{8}$ & rd = rd $-$ i$^{\emptyset}_{ }$ & S \\
SUB\{S\} & rd, rn, rm & rd = rn $-$ rm & S \\
SUB & SP, \#i$^{ }_{9}$ & SP = SP $-$ i$^{\emptyset}_{8:2}$:0$^{ }_{2}$ & \\
\end{asmtable}
%
\begin{asmtable}{Thumb16 Load and Store Instructions}
LDM\textit{IA} & rn\{!\}, rlist & rlist = [rn]$^{ }_{32cnt}$; if(!) rn $+$= 4cnt & \\
LDMIA & SP!, rlist & rlist = [SP]$^{ }_{32cnt}$; SP $+$= 4cnt & \\
LDR & rt, [rn\{, \#i$^{ }_{7}$\}] & rt = [rn $+$ i$^{\emptyset}_{6:2}$:0$^{ }_{2}$]$^{ }_{32}$ & \\
LDR & rt, [SP\{, \#i$^{ }_{10}$\}] & rt = [SP $+$ i$^{\emptyset}_{9:2}$:0$^{ }_{2}$]$^{ }_{32}$ & \\
LDR & rt, rel$^{ }_{10}$ & rt = [PC $+$ rel$^{\emptyset}_{9:2}$:0$^{ }_{2}$]$^{ }_{32}$ & \\
LDR & rt, [rn, rm] & rt = [rn $+$ rm]$^{ }_{32}$ & \\
LDRB & rt, [rn\{, \#i$^{ }_{5}$\}] & rt = [rn $+$ i$^{\emptyset}_{ }$]$^{\emptyset}_{8}$ & \\
LDRB & rt, [rn, rm] & rt = [rn $+$ rm]$^{\emptyset}_{8}$ & \\
LDRH & rt, [rn\{, \#i$^{ }_{6}$\}] & rt = [rn $+$ i$^{\emptyset}_{5:1}$:0$^{ }_{1}$]$^{\emptyset}_{16}$ & \\
LDRH & rt, [rn, rm] & rt = [rn $+$ rm]$^{\emptyset}_{16}$ & \\
LDRSB & rt, [rn, rm] & rt = [rn $+$ rm]$^{\pm}_{8}$ & \\
LDRSH & rt, [rn, rm] & rt = [rn $+$ rm]$^{\pm}_{16}$ & \\
\textit{POP} & rlist & rlist = [SP]$^{ }_{32cnt}$; SP $+$= 4cnt & \\
\textit{PUSH} & rlist & SP $-$= 4cnt; [SP]$^{ }_{32cnt}$ = rlist & \\
STM\textit{IA} & rn!, rlist & [rn]$^{ }_{32cnt}$ = rlist; rn $+$= 4cnt & \\
STMDB & SP!, rlist & SP $-$= 4cnt; [SP]$^{ }_{32cnt}$ = rlist & \\
STR & rt, [rn\{, \#i$^{ }_{7}$\}] & [rn $+$ i$^{\emptyset}_{6:2}$:0$^{ }_{2}$]$^{ }_{32}$ = rt & \\
STR & rt, [SP\{, \#i$^{ }_{10}$\}] & [SP $+$ i$^{\emptyset}_{9:2}$:0$^{ }_{2}$]$^{ }_{32}$ = rt & \\
STR & rt, [rn, rm] & [rn $+$ rm]$^{ }_{32}$ = rt & \\
STRB & rt, [rn\{, \#i$^{ }_{5}$\}] & [rn $+$ i$^{\emptyset}_{ }$]$^{ }_{8}$ = rt$^{ }_{B0}$ & \\
STRB & rt, [rn, rm] & [rn $+$ rm]$^{ }_{8}$ = rt$^{ }_{B0}$ & \\
STRH & rt, [rn\{, \#i$^{ }_{6}$\}] & [rn $+$ i$^{\emptyset}_{5:1}$:0$^{ }_{1}$]$^{ }_{16}$ = rt$^{ }_{H0}$ & \\
STRH & rt, [rn, rm] & [rn $+$ rm]$^{ }_{16}$ = rt$^{ }_{H0}$ & \\
\end{asmtable}
%
\newpage
\begin{center}
{\Large\bfseries AArch32 Floating-point and \\* Advanced SIMD Extensions}
\end{center}
%
\begin{asmtable2}{Floating-point Arithmetic Instructions}
VABS.f & fd, fn & fd = $\lvert$fn$\rvert$ & \\
VADD.f & fd, fn, fm & fd = fn $+$ fm & \\
VCMP\{E\}.f & fn, \#0.0 & FPSCR\_nzcv = Compare(fn, 0.0) & \\
VCMP\{E\}.f & fn, fm & FPSCR\_nzcv = Compare(fn, fm) & \\
VDIV.f & fd, fn, fm & fd = fn $\udiv$ fm & \\
VFMa.f & fd, fn, fm & fd = fd $\pm$ fn $\umul$ fm & V4 \\
VFMNa.f & fd, fn, fm & fd = $-$fd $\pm$ fn $\umul$ fm & V4 \\
VMAXNM.f & fd, fn, fm & fd = fn $\max$ fm & 8,I \\
VMINNM.f & fd, fn, fm & fd = fn $\min$ fm & 8,I \\
VMLa.f & fd, fn, fm & fd = fd $\pm$ fn $\umul$ fm & \\
VMUL.f & fd, fn, fm & fd = fn $\umul$ fm & \\
VNEG.f & fd, fn & fd = 0.0 $-$ fn & \\
VNMLa.f & fd, fn, fm & fd = $-$fd $\pm$ $-$fn $\umul$ fm & \\
VNMUL.f & fd, fn, fm & fd = 0.0 $-$ fn $\umul$ fm & \\
VSQRT.f & fd, fn & fd = SQRT(fn) & \\
VSUB.f & fd, fn, fm & fd = fn $-$ fm & \\
\end{asmtable2}
%
\begin{asmtable2}{Load/Store Instructions}
VLDMDB\{.z\} & rn\{!\}, flist & flist=[rn$-^{z}_{8}$cnt]$^{ }_{z{\times}cnt}$; if(!) rn$-$=$^{z}_{8}$cnt & \\
VLDM\textit{IA}\{.z\} & rn\{!\}, flist & flist = [rn]$^{ }_{z{\times}cnt}$; if(!) rn $+$= $^{z}_{8}\times$cnt & \\
VLDR.16 & St,[rn\{,\#i$^{ }_{9}$\}] & St = [rn $+$ i$^{\pm}_{8:1}$:0$^{ }_{1}$]$^{\emptyset}_{16}$ & 8{\tiny 2} \\
VLDR\{.z\} & ft,[rn\{,\#i$^{ }_{10}$\}] & ft = [rn $+$ i$^{\pm}_{9:2}$:0$^{ }_{2}$]$^{ }_{z}$ & \\
VLDR.16 & St, rel$^{ }_{9}$ & St = [PC $+$ rel$^{\pm}_{8:1}$:0$^{ }_{1}$]$^{\emptyset}_{16}$ & 8{\tiny 2} \\
VLDR\{.z\} & ft, rel$^{ }_{10}$ & ft = [PC $+$ rel$^{\pm}_{9:2}$:0$^{ }_{2}$]$^{ }_{z}$ & \\
\textit{VPOP\{.z\}} & flist & SP $-$= $^{z}_{8}\times$cnt; flist = [SP]$^{ }_{z{\times}cnt}$ & \\
\textit{VPUSH\{.z\}} & flist & [SP]$^{ }_{z{\times}cnt}$ = flist; SP $+$= $^{z}_{8}\times$cnt & \\
VSTMDB\{.z\} & rn\{!\}, flist & [rn$-^{z}_{8}\times$cnt]$^{ }_{f{\times}cnt}$=flist; if(!)rn$-$=$^{z}_{8}\times$cnt & \\
VSTM\textit{IA}\{.z\} & rn\{!\}, flist & [rn]$^{ }_{z{\times}cnt}$ = flist; if(!) rn $+$= $^{z}_{8}\times$cnt & \\
VSTR.16 & St,[rn\{,\#i$^{ }_{9}$\}] & [rn $+$ i$^{\pm}_{8:1}$:0$^{ }_{1}$]$^{ }_{16}$ = St$^{ }_{H0}$ & 8{\tiny 2} \\
VSTR\{.z\} & ft,[rn\{,\#i$^{ }_{10}$\}] & [rn $+$ i$^{\pm}_{9:2}$:0$^{ }_{2}$]$^{ }_{z}$ = ft & \\
\end{asmtable2}
%
\begin{asmtable2}{Floating-point Convertion Instructions}
VCVT.F32.F64 & Sd, Dn & Sd = Float2Float(Dn) & \\
VCVT.F64.F32 & Dd, Sn & Dd = Float2Float(Sn) & \\
VCVT.sz.f & fd, fn, \#i$^{ }_{5}$ & fd = Float2Fixed(fn, i)$^{s}_{ }$ & V3 \\ % z = 16,32
VCVT.f.s32 & fd, Sn & fd = Int2Float(Sn$^{s}_{ }$) & \\
VCVT.f.sz & fd, fn, \#i$^{ }_{5}$ & fd = Fixed2Float(fn$^{s}_{ }$, i) & V3 \\ % z = 16,32
VCVT\{,R\}.s32.f & Sd, fn & Sd = Float2Int(fn)$^{s}_{ }$ & \\
VCVTx.F16.F32 & Sd, Sn & Sd$^{ }_{Hx}$ = Float2Float(Sn) & V3 \\
VCVTx.F32.F16 & Sd, Sn & Sd = Float2Float(Sn$^{ }_{Hx}$) & V3 \\
VRINT\{r,R,Z\}.f & fd, fn & fd = Rount2Int(fn, \{r,R,Z\}) & 8,I \\
VRINTX.f & fd, fn & fd = Rount2IntExact(fn, FPSCR) & 8,I \\
\end{asmtable2}
%
\begin{asmtable6}{Register Transfer Instructions}
VINS.F16 & Sd, Sn & Sd = Sn$^{ }_{H0}$:Sd$^{ }_{H0}$ & 8{\tiny 2},I \\
VMOV\{.32\} & Dd[i], rn & Dd$^{ }_{32i}$ = rn & \\
VMOV\{.32\} & rd, Dn[i] & rd = Dn$^{ }_{32i}$ & \\
VMOV & Sd, rn & Sd = rn & \\
VMOV & rd, Sn & rd = Sn & \\
VMOV & Sd, Sd$^{'}_{ }$, rn, rm & Sd$^{'}_{ }$:Sd = rm:rn & \\
VMOV & rd, rd2, Sn, Sn$^{'}_{ }$ & rd2:rd = Sn$^{'}_{ }$:Sn & \\
VMOV & Dd, rn, rm & Dd = rm:rn & \\
VMOV & rd, rd2, Dn & rd2:rd = Dn & \\
VMOV.f & fd, \#i & fd = i & V3 \\
VMOV.f & fd, fn & fd = fn & \\
VMOV.F16 & Sd, rn & Sd = rn$^{\emptyset}_{H0}$ & 8{\tiny 2},I \\
VMOV.F16 & rd, Sn & rd = Sn$^{\emptyset}_{H0}$ & 8{\tiny 2},I \\
VMOVX.F16 & Sd, Sn & Sd = Sn$^{\emptyset}_{H1}$ & 8{\tiny 2},I \\
VMRS & rd, fpreg & rd = fpreg & \\
VMRS & APSR\_nzcv,FPSCR & APSR\_nzcv = FPSCR\_nzcv & \\
VMSR & fpreg, rn & fpreg = rn & \\
VSELcs & fd, fn, fm & fd = (cs) ? fn : fm & 8,I \\
\end{asmtable6}
%
\begin{table-lX}{Floating-point System Registers (fpreg)}
FPEXC & Floating-point Exception Control \\
FPSCR & Floating-point Status and Control \\
FPSID & Floating-point System ID \\
MVFR\{0..2\} & Media and VFP Feature \{0..2\} \\
\end{table-lX}
%
\begin{table-llXr}{Floating-point Status and Control Register (FPSCR)}
DOE,IOC & 0x00000101 & Invalid operation (trap enable, exception) & \\
DZE,DZC & 0x00000202 & Division by zero (trap enable, exception) & \\
OFE,OFC & 0x00000404 & Overflow (trap enable, exception) & \\
UFE,UFC & 0x00000808 & Underflow (trap enable, exception) & \\
IXE,IXC & 0x00001010 & Inexact (trap enable, exception) & \\
IDE,IDC & 0x00008080 & Input denormal (trap enable, exception) & \\
%Len & 0x00070000 & VFP vector length & \\ % Deprecated
FZ16 & 0x00080000 & Flush-to-zero mode for half-precision & 8{\tiny 2} \\
%Stride & 0x00300000 & VFP vector stride & \\ % Deprecated
RMode & 0x00c00000 & Rounding mode (RN,RP,RM,RZ) & \\
FZ & 0x01000000 & Flush-to-zero mode & \\
DN & 0x02000000 & Default NaN mode & \\
AHP & 0x04000000 & Alternative half-precision & \\
QC & 0x08000000 & Cumulative saturation & \\
N,Z,C,V & 0xf0000000 & Condition flags (Negative,Zero,Carry,Overflow) & \\
\end{table-llXr}
%
\begin{table-lX}{Notes for Floating-point and SIMD Instructions}
V3,V4 & Introduced in VFPv3, VFPv4 \\
SH,S2 & Introduced in SIMD with half-precision floats, SIMDv2 \\
8,8{\tiny 1},8{\tiny 2} & Introduced in ARMv8, ARMv8.1, or ARMv8.2 \\
F & Data type F16 (8{\tiny 2} only), F32, and sometimes F64 also allowed \\
I & Can't be conditional \\
\end{table-lX}
%
\begin{asmtable}{SIMD Load/Store Instructions}
VLD1.z & \{Dt...\}, [addr] & ...:Dt$^{'}_{ }$:Dt = [addr]$^{ }_{64 \umul cnt}$ & \\ % z = 8,16,32,64
VLD1.z & \{Dt[]...\}, [addr] & (...:Dt$^{'}_{ }$:Dt)$^{ }_{z*}$ = [addr]$^{ }_{z}$ & \\ % z = 8,16,32
VLD1.z & \{Dt[i]\}, [addr] & Dt$^{ }_{zi}$ = [addr]$^{ }_{z}$ & \\ % z = 8,16,32
VLD2.z & \{Dt...\}, [addr] & ...:Dt$^{ }_{z2}$:Dt$^{'}_{z1}$:Dt$^{ }_{z1}$:Dt$^{'}_{z0}$:Dt$^{ }_{z0}$=[addr]$^{ }_{64 \umul cnt}$ & \\ % z = 8,16,32
VLD2.z & \{Dt[]...\}, [addr] & Dt$^{'}_{z*}$:Dt$^{ }_{z*}$ = [addr]$^{ }_{2z}$ & \\ % z = 8,16,32
VLD2.z & \{Dt[i]...\}, [addr] & Dt$^{'}_{zi}$:Dt$^{ }_{zi}$ = [addr]$^{ }_{2z}$ & \\ % z = 8,16,32
VLD3.z & \{Dt...\}, [addr] & ...:Dt$^{'}_{z1}$:Dt$^{ }_{z1}$:Dt$^{''}_{z0}$:Dt$^{'}_{z0}$:Dt$^{ }_{z0}$=[addr]$^{ }_{64 \umul cnt}$ & \\ % z = 8,16,32
VLD3.z & \{Dt[]...\}, [addr] & Dt$^{''}_{z*}$:Dt$^{'}_{z*}$:Dt$^{ }_{z*}$ = [addr]$^{ }_{3z}$ & \\ % z = 8,16,32
VLD3.z & \{Dt[i]...\}, [addr] & Dt$^{''}_{zi}$:Dt$^{'}_{zi}$:Dt$^{ }_{zi}$ = [addr]$^{ }_{3z}$ & \\ % z = 8,16,32
VLD4.z & \{Dt...\}, [addr] & ...:Dt$^{ }_{z1}$:Dt$^{'''}_{z0}$:Dt$^{''}_{z0}$:Dt$^{'}_{z0}$:Dt$^{ }_{z0}$=[addr]$^{ }_{64 \umul cnt}$ & \\ % z = 8,16,32
VLD4.z & \{Dt[]...\}, [addr] & Dt$^{'''}_{z*}$:Dt$^{''}_{z*}$:Dt$^{'}_{z*}$:Dt$^{ }_{z*}$ = [addr]$^{ }_{4z}$ & \\ % z = 8,16,32
VLD4.z & \{Dt[i]...\}, [addr] & Dt$^{'''}_{zi}$:Dt$^{''}_{zi}$:Dt$^{'}_{zi}$:Dt$^{ }_{zi}$ = [addr]$^{ }_{4z}$ & \\ % z = 8,16,32
VST1.z & \{Dt...\}, [addr] & [addr]$^{ }_{64 \umul cnt}$ = ...:Dt$^{'}_{ }$:Dt & \\ % z = 8,16,32,64
VST1.z & \{Dt[i]\}, [addr] & [addr]$^{ }_{z}$ = Dt$^{ }_{zi}$ & \\ % z = 8,16,32
VST2.z & \{Dt...\}, [addr] & [addr]$^{ }_{64 \umul cnt}$ = ...:Dt$^{'}_{z1}$:Dt$^{ }_{z1}$:Dt$^{'}_{z0}$:Dt$^{ }_{z0}$ & \\ % z = 8,16,32
VST2.z & \{Dt[i]...\}, [addr] & [addr]$^{ }_{2z}$ = Dt$^{'}_{zi}$:Dt$^{ }_{zi}$ & \\ % z = 8,16,32
VST3.z & \{Dt...\}, [addr] & [addr]$^{ }_{64 \umul cnt}$=...:Dt$^{'}_{z1}$:Dt$^{ }_{z1}$:Dt$^{''}_{z0}$:Dt$^{'}_{z0}$:Dt$^{ }_{z0}$ & \\ % z = 8,16,32
VST3.z & \{Dt[i]...\}, [addr] & [addr]$^{ }_{3z}$ = Dt$^{''}_{zi}$:Dt$^{'}_{zi}$:Dt$^{ }_{zi}$ & \\ % z = 8,16,32
VST4.z & \{Dt...\}, [addr] & [addr]$^{ }_{64 \umul cnt}$=...:Dt$^{ }_{z1}$:Dt$^{'''}_{z0}$:Dt$^{''}_{z0}$:Dt$^{'}_{z0}$:Dt$^{ }_{z0}$ & \\ % z = 8,16,32
VST4.z & \{Dt[i]...\}, [addr] & [addr]$^{ }_{4z}$ = Dt$^{'''}_{zi}$:Dt$^{''}_{zi}$:Dt$^{'}_{zi}$:Dt$^{ }_{zi}$ & \\ % z = 8,16,32
\end{asmtable}
%
\begin{table-lX}{VLDx/VSTx Addressing Modes}
rn\{:align\} & addr = rn \\
rn\{:align\}! & addr = rn; rn $+$= (z$\lsr$3) $\times$ cnt \\
rn\{:align\}, rm & addr = rn; rn $+$= rm \\
\end{table-lX}
%
\begin{asmtable}{SIMD Register Transfer Instructions}
VDUP.z & md, rn & md$^{ }_{z*}$ = rn$^{ }_{z}$ & \\ % z = 8,16,32
VDUP.z & md, Dn[i] & md$^{ }_{z*}$ = Dn$^{ }_{zi}$ & \\ % z = 8,16,32
VMOV.z & Dd[i], rn & Dd$^{ }_{zi}$ = rn$^{ }_{z}$ & \\ % z = 8,16
VMOV.sz & rd, Dn[i] & rd = Dn$^{s}_{zi}$ & \\ % z = 8,16
\textit{VMOV} & md, mn & md = mn & \\
VSWP & md, mn & mn:md = md:mn & \\
\end{asmtable}
%
\begin{table-lX}{Floating-point and SIMD Keys}
z & Data size (8, 16, 32, or (sometimes) 64) \\
f & Floating-point size (F16 (8{\tiny 2} only), F32, or F64) \\
Sd, Dn, Qm & Singleword/doubleword/quadword register \\
fd, fn, fm & Floating-point register (Sx or Dx depending on data size) \\
md, mn, mm & SIMD register (Dx or Qx) \\
cm & SIMD comparison operator (GE, GT, LE, or LT) \\
cs & Floating-point comparison operator (EQ, GE, GT, or VS) \\
r & Rounding (A, M, N, or P) \\
x $\lsl\lsr$ y & (y $\ult$ 0) ? (x $\lsr$ $-$y) : (x $\lsl$ y) \\
$\max$ $\min$ & Maximum/minimum value \\
\end{table-lX}
%
\begin{asmtable2}{SIMD Addition and Subtraction Instructions}
VABA.sz & md, mn, mm & md$^{ }_{z*}$ $+$= $\lvert$mn$^{ }_{z*}$ $-$ mm$^{ }_{z*}$$\rvert$ & \\ % z = 8,16,32
VABAL.sz & Qd, Dn, Dm & Qd$^{ }_{2z*}$ $+$= $\lvert$Dn$^{ }_{z*}$ $-$ Dm$^{ }_{z*}$$\rvert$ & \\ % z = 8,16,32
VABD.sz & md, mn, mm & md$^{ }_{z*}$ = $\lvert$mn$^{ }_{z*}$ $-$ mm$^{ }_{z*}$$\rvert$ & F \\ % z = 8,16,32
VABDL.sz & Qd, Dn, Dm & Qd$^{ }_{2z*}$ = $\lvert$Dn$^{ }_{z*}$ $-$ Dm$^{ }_{z*}$$\rvert$ & \\ % z = 8,16,32
VABS.Sz & md, mn & md$^{ }_{z*}$ = $\lvert$mn$^{ }_{z*}$$\rvert$ & F \\ % z = 8,16,32
VADD.Iz & md, mn, mm & md$^{ }_{z*}$ = mn$^{ }_{z*}$ $+$ mm$^{ }_{z*}$ & F \\ % z = 8,16,32,64
VADDL.sz & Qd, Dn, Dm & Qd$^{ }_{z*}$ = Dn$^{s}_{z*}$ $+$ Dm$^{s}_{z*}$ & \\ % z = 8,16,32
VADDW.sz & Qd, Qn, Dm & Qd$^{ }_{z*}$ = Qn$^{ }_{z*}$ $+$ Dm$^{s}_{z*}$ & \\ % z = 8,16,32
VHSUB.sz & md, mn, mm & md$^{ }_{z*}$ = (mn$^{s}_{z*}$ $-$ mm$^{s}_{z*}$) $\lsr$ 1 & \\ % z = 8,16,32
VNEG.Sz & md, mn & md$^{ }_{z*}$ = 0 $-$ mn$^{ }_{z*}$ & F \\ % z = 8,16,32
VPADAL.sz & md, mn & md$^{ }_{2z*}$ $+$= mn$^{s}_{z2*}$ $+$ mn$^{s}_{z2*+1}$ & \\ % z = 8,16,32
VPADD.Iz & Dd, Dn, Dm & Dd$^{ }_{z*}$ = (Dm:Dn)$^{ }_{z2*}$ $+$ (Dm:Dn)$^{ }_{z2*+1}$ & F \\ % z = 8,16,32
VPADDL.sz & md, mn & md$^{ }_{2z*}$ = mn$^{s}_{z2*}$ $+$ mn$^{s}_{z2*+1}$ & \\ % z = 8,16,32
V\{R\}ADDHN.Iz & Dd, Qn, Qm & Dd$^{ }_{0\text{.}5z*}$ = Qn$^{ }_{z*}$ $+$ Qm$^{ }_{z*}$ $\lsr^{\{R\}}_{ }$ z & \\ % z = 16,32,64
V\{R\}HADD.sz & md, mn, mm & md$^{ }_{z*}$ = (mn$^{s}_{z*}$ $+$ mm$^{s}_{z*}$) $\lsr^{\{R\}}_{ }$ 1 & \\ % z = 8,16,32
V\{R\}SUBHN.Iz & Dd, Qn, Qm & Dd$^{ }_{0\text{.}5z*}$ = Qn$^{ }_{z*}$ $-$ Qm$^{ }_{z*}$ $\lsr^{\{R\}}_{ }$ z & \\ % z = 16,32,64
VQABS.Sz & md, mn & md$^{ }_{z*}$ = $\lfloor$ $\lvert$mn$^{ }_{z*}$$\rvert$ $\rceil^{Sz}$ & \\ % z = 8,16,32
VQADD.sz & md, mn, mm & md$^{ }_{z*}$ = $\lfloor$mn$^{ }_{z*}$ $+$ mm$^{ }_{z*}$$\rceil^{sz}$ & \\ % z = 8,16,32,64
VQNEG.Sz & md, mn & md$^{ }_{z*}$ = $\lfloor$0 - mn$^{ }_{z*}$$\rceil^{Sz}$ & \\ % z = 8,16,32
VQSUB.sz & md, mn, mm & md$^{ }_{z*}$ = $\lfloor$mn$^{ }_{z*}$ $-$ mm$^{ }_{z*}$$\rceil^{sz}$ & \\ % z = 8,16,32,64
VSUB.Iz & md, mn, mm & md$^{ }_{z*}$ = mn$^{ }_{z*}$ $-$ mm$^{ }_{z*}$ & F \\ % z = 8,16,32,64
VSUBL.sz & Qd, Dn, Dm & Qd$^{ }_{z*}$ = Dn$^{s}_{z*}$ $-$ Dm$^{s}_{z*}$ & \\ % z = 8,16,32
VSUBW.sz & Qd, Qn, Dm & Qd$^{ }_{z*}$ = Qn$^{ }_{z*}$ $-$ Dm$^{s}_{z*}$ & \\ % z = 8,16,32
\end{asmtable2}
%
\begin{asmtable4}{SIMD Bitwise Instructions}
VAND & md, mn, mm & md = mn \& mm & \\
\textit{VAND.Iz} & md, \#i & md$^{ }_{z*}$ = md$^{ }_{z*}$ \& i & \\ % z = 8,16,32,64
VBIC & md, mn, mm & md = mn \& $\sim$mm & \\
VBIC.Iz & md, \#i & md$^{ }_{z*}$ = md$^{ }_{z*}$ \& $\sim$i & \\ % z = 16,32 (8,64 as instruction alias)
VBIF & md, mn, mm & if(mm$^{ }_{1*}$ $=$ 0) md$^{ }_{1*}$ = mn$^{ }_{1*}$ & \\
VBIT & md, mn, mm & if(mm$^{ }_{1*}$ $=$ 1) md$^{ }_{1*}$ = mn$^{ }_{1*}$ & \\
VBSL & md, mn, mm & md$^{ }_{1*}$ = (md$^{ }_{1*}$ $\eq$ 1) ? mn$^{ }_{1*}$ : mm$^{ }_{1*}$ & \\
VCLS.Sz & md, mn & md$^{ }_{z*}$ = CountLeadingSignBits(mn$^{ }_{z*}$) & \\ % z = 8,16,32
VCLZ.Iz & md, mn & md$^{ }_{z*}$ = CountLeadingZeros(mn$^{ }_{z*}$) & \\ % z = 8,16,32
VCNT.8 & md, mn & md$^{ }_{8*}$ = CountOneBits(mn$^{ }_{8*}$) & \\
VEOR & md, mn, mm & md = mn $\oplus$ mm & \\
VEXT.z & md,mn,mm,\#i$^{ }_{4}$ & md$^{ }_{z*}$ = mm$^{ }_{z*[i-1:0]}$:mn$^{ }_{z*[z-1:z-i+1]}$ & \\
VMOV.Iz & md, \#i & md$^{ }_{z*}$ = i & F \\ % z = 8,16,32,64
VMVN & md, mn & md = $\sim$mn & \\
VMVN.Iz & md, \#i & md$^{ }_{z*}$ = $\sim$i & \\ % z = 16,32
VORR & md, mn, mm & md = mn | mm & \\
VORR.Iz & md, \#i & md$^{ }_{z*}$ = md$^{ }_{z*}$ | i & \\ % z = 16,32 (8,64 as instruction alias)
VORN & md, mn, mm & md = mn | $\sim$mm & \\
\textit{VORN.Iz} & md, \#i & md$^{ }_{z*}$ = md$^{ }_{z*}$ | $\sim$i & \\ % z = 8,16,32,64
\end{asmtable4}
%
\begin{asmtable2}{SIMD Multiply Instructions}
VFMa.F32 & md, mn, mm & md$^{ }_{z*}$ $\pm$= mn$^{ }_{z*}$ $\umul$ mm$^{ }_{z*}$ & S2 \\
VMLa.Iz & md, mn, mm & md$^{ }_{z*}$ $\pm$= mn$^{ }_{z*}$ $\umul$ mm$^{ }_{z*}$ & F \\ % z = 8,16,32
VMLa.Iz & md,mn,Dm[i] & md$^{ }_{z*}$ $\pm$= mn$^{ }_{z*}$ $\umul$ Dm$^{ }_{zi}$ & F \\ % z = 16,32
VMLaL.sz & Qd, Dn, Dm & Qd$^{ }_{2z*}$ $\pm$= Dn$^{ }_{z*}$ $\umul^{s}_{ }$ Dm$^{ }_{z*}$ & \\ % z = 8,16,32
VMLaL.sz & Qd,Dn,Dm[i] & Qd$^{ }_{2z*}$ $\pm$= Dn$^{ }_{z*}$ $\umul^{s}_{ }$ Dm$^{ }_{zi}$ & \\ % z = 16,32
VMUL.Iz & md, mn, mm & md$^{ }_{z*}$ = mn$^{ }_{z*}$ $\umul$ mm$^{ }_{z*}$ & F \\ % z = 8,16,32
VMUL.Iz & md,mn,Dm[i] & md$^{ }_{z*}$ = mn$^{ }_{z*}$ $\umul$ Dm$^{ }_{zi}$ & F \\ % z = 16,32
VMUL.P8 & md, mn, mm & md$^{ }_{8*}$ = mn$^{ }_{8*}$ $\ast$ mm$^{ }_{8*}$ & \\
VMULL.P8 & Qd, Dn, Dm & Qd$^{ }_{16*}$ = Dn$^{ }_{8*}$ $\ast$ Dm$^{ }_{8*}$ & \\
VMULL.P64 & Qd, Dn, Dm & Qd = Dn $\ast$ Dm & 8,I \\
VMULL.sz & Qd, Dn, Dm & Qd$^{ }_{2z*}$ = Dn$^{ }_{z*}$ $\umul^{s}_{ }$ Dm$^{ }_{z*}$ & \\ % z = 8,16,32
VMULL.sz & Qd,Dn,Dm[i] & Qd$^{ }_{2z*}$ = Dn$^{ }_{z*}$ $\umul^{s}_{ }$ Dm$^{ }_{zi}$ & \\ % z = 16,32
VQDMLaL.Sz & Qd, Dn, Dm & Qd$^{ }_{2z*}$ $\pm$= $\lfloor$2 $\smul$ Dn$^{ }_{z*}$ $\smul$ Dm$^{ }_{z*}$$\rceil^{Sz}$ & \\ % z = 16,32
VQDMLaL.Sz & Qd,Dn,Dm[i] & Qd$^{ }_{2z*}$ $\pm$= $\lfloor$2 $\smul$ Dn$^{ }_{z*}$ $\smul$ Dm$^{ }_{zi}$$\rceil^{Sz}$ & \\ % z = 16,32
VQDMULH.Sz & md, mn, mm & md$^{ }_{z*}$ = $\lfloor$(2 $\smul$ mn$^{ }_{z*}$ $\smul$ mm$^{ }_{z*}$) $\asr$ z$\rceil^{S2z}$ & \\ % z = 16,32
VQDMULH.Sz & md,mn,Dm[i] & md$^{ }_{z*}$ = $\lfloor$(2 $\smul$ mn$^{ }_{z*}$ $\smul$ Dm$^{ }_{zi}$) $\asr$ z$\rceil^{S2z}$ & \\ % z = 16,32
VQDMULL.Sz & Qd, Dn, Dm & Qd$^{ }_{2z*}$ = $\lfloor$2 $\smul$ Dn$^{ }_{z*}$ $\smul$ Dm$^{ }_{z*}$$\rceil^{S2z}$ & \\ % z = 16,32
VQDMULL.Sz & Qd,Dn,Dm[i] & Qd$^{ }_{2z*}$ = $\lfloor$2 $\smul$ Dn$^{ }_{z*}$ $\smul$ Dm$^{ }_{zi}$$\rceil^{S2z}$ & \\ % z = 16,32
VQRDMLaH.Sz & md, mn, mm & md$^{ }_{z*}$=$\lfloor$md$^{ }_{z*}$$\lsl$z$\pm$2$\smul$mn$^{ }_{z*}$$\smul$mm$^{ }_{z*}$$\asr^{R}_{ }$z$\rceil^{Sz}$ & 8{\tiny 1},I \\ % z = 16,32
VQRDMLaH.Sz & md,mn,Dm[i] & md$^{ }_{z*}$=$\lfloor$md$^{ }_{z*}$$\lsl$z$\pm$2$\smul$mn$^{ }_{z*}$$\smul$Dm$^{ }_{zi}$$\asr^{R}_{ }$z$\rceil^{Sz}$) & 8{\tiny 1},I \\ % z = 16,32
VQRDMULH.Sz & md, mn, mm & md$^{ }_{z*}$=$\lfloor$(2 $\smul$ mn$^{ }_{z*}$ $\smul$ mm$^{ }_{z*}$) $\asr^{R}_{ }$ z$\rceil^{S2z}$ & \\ % z = 16,32
VQRDMULH.Sz & md,mn,Dm[i] & md$^{ }_{z*}$=$\lfloor$(2 $\smul$ mn$^{ }_{z*}$ $\smul$ Dm$^{ }_{zi}$) $\asr^{R}_{ }$ z$\rceil^{S2z}$ & \\ % z = 16,32
\end{asmtable2}
%
\begin{asmtable2}{SIMD Misc Processing Instructions}
VRECPE.U32 & md, mn & md$^{ }_{32*}$ = RecipEstimate(mn$^{ }_{32*}$) & F \\
VRECPS.F32 & md, mn, mm & md$^{ }_{32*}$ = RecipStep(mn$^{ }_{32*}$, mm$^{ }_{32*}$) & \\
VREV16.8 & md, mn & md$^{ }_{16*}$ = mn$^{ }_{16*[B0]}$:mn$^{ }_{16*[B1]}$ & \\
VREV32.8 & md, mn & md$^{ }_{32*}$ = mn$^{ }_{32*[B0]}$:..:mn$^{ }_{32*[B3]}$ & \\
VREV32.16 & md, mn & md$^{ }_{32*}$ = mn$^{ }_{32*[H0]}$:mn$^{ }_{32*[H1]}$ & \\
VREV64.8 & md, mn & md$^{ }_{64*}$ = mn$^{ }_{64*[B0]}$:...:mn$^{ }_{64*[B7]}$ & \\
VREV64.16 & md, mn & md$^{ }_{64*}$ = mn$^{ }_{64*[H0]}$:...:mn$^{ }_{64*[H3]}$ & \\
VREV64.32 & md, mn & md$^{ }_{64*}$ = mn$^{ }_{64*[31:0]}$:mn$^{ }_{64*[63:32]}$ & \\
VRSQRTE.U32 & md, mn & md$^{ }_{32*}$ = SqrtEstimate(mn$^{ }_{32*}$) & F \\
VRSQRTS.F32 & md, mn, mm & md$^{ }_{32*}$ = SqrtStep(mn$^{ }_{32*}$, mm$^{ }_{32*}$) & \\
VTBL.8 & Dd,{Dn...},Dm & Dd$^{ }_{8*}$= Dm$^{ }_{8*}$$\ult$cnt$\umul$8 ?(Dn:...)$^{ }_{8Dm^{ }_{8*}}$ :0 & \\
VTBX.8 & Dd,{Dn...},Dm & if(Dm$^{ }_{8*}$$\ult$cnt$\umul$8) Dd$^{ }_{8*}$=(Dn:...)$^{ }_{8Dm^{ }_{8*}}$ & \\
VTRN.z & md, mn & if(even) mn$^{ }_{z*}$:md$^{ }_{z*+1}$ = md$^{ }_{z*+1}$:mn$^{ }_{z*}$ & \\ % z = 8,16,32
VUZP.z & md, mn & mn = ...:mn$^{ }_{z3}$:mn$^{ }_{z1}$:...:md$^{ }_{z3}$:md$^{ }_{z1}$ \newline md = ...:mn$^{ }_{z2}$:mn$^{ }_{z0}$:...:md$^{ }_{z2}$:md$^{ }_{z0}$ & \\ %z!=64
VZIP.z & md, mn & mn:md = ...:mn$^{ }_{z1}$:md$^{ }_{z1}$:mn$^{ }_{z0}$:md$^{ }_{z0}$ & \\ % z = 8,16,32
\end{asmtable2}
%
\begin{asmtable5}{SIMD Shift Instructions}
VQSHL.sz & md, mn, \#i$^{ }_{5}$ & md$^{ }_{z*}$ = $\lfloor$mn$^{ }_{z*}$ $\lsl$ i$\rceil^{sz}$ & \\ % z = 8,16,32,64
VQ\{R\}SHL.sz & md, mn, mm & md$^{ }_{z*}$ = $\lfloor$mn$^{ }_{z*}$ $\lsl\lsr^{s \{R\}}_{ }$ mm$^{ }_{z*}\rceil^{sz}$ & \\ % z = 8,16,32,64
VQSHLU.Sz & md, mn, \#i$^{ }_{5}$ & md$^{ }_{z*}$ = $\lfloor$mn$^{ }_{z*}$ $\lsl\asr$ i$\rceil^{Uz}$ & \\ % z = 8,16,32,64
VQ\{R\}SHRN.sz & Dd, Qn, \#i$^{ }_{5}$ & Dd$^{ }_{0\text{.}5z*}$ = $\lfloor$Qn$^{ }_{z*}$ $\lsr^{s \{R\}}_{ }$ i$\rceil^{sz}$ & \\ % z = 16,32,64
VQ\{R\}SHRUN.Sz & Dd, Qn, \#i$^{ }_{5}$ & Dd$^{ }_{0\text{.}5z*}$ = $\lfloor$Qn$^{ }_{z*}$ $\asr^{\{R\}}_{ }$ i$\rceil^{Uz}$ & \\ % z = 16,32,64
VSHL.Iz & md, mn, \#i$^{ }_{6}$ & md$^{ }_{z*}$ = mn$^{ }_{z*}$ $\lsl$ i & \\ % z = 8,16,32,64
V\{R\}SHL.sz & md, mn, mm & md$^{ }_{z*}$ = mn$^{ }_{z*}$ $\lsl\lsr^{s \{R\}}_{ }$ mm$^{ }_{z*}$ & \\ % z = 8,16,32,64
VSHLL.Iz & Qd, Dn, \#i$^{ }_{5}$ & Qd$^{ }_{2z*}$ = Dn$^{ }_{z*}$ $\lsl$ i & \\ % z = 8,16,32
VSHLL.sz & Qd, Dn, \#i$^{ }_{5}$ & Qd$^{ }_{0\text{.}5z*}$ = Dn$^{ }_{z*}$ $\lsl$ i & \\ % z = 8,16,32
V\{R\}SHR.sz & md, mn, \#i$^{ }_{6}$ & md$^{ }_{z*}$ = mn$^{ }_{z*}$ $\lsr^{s \{R\}}_{ }$ i & \\ % z = 8,16,32,64
V\{R\}SHRN.Iz & Dd, Qn, \#i$^{ }_{5}$ & Dd$^{ }_{0\text{.}5z*}$ = Qn$^{ }_{z*}$ $\lsr^{\{R\}}_{ }$ i & \\ % z = 16,32,64
VSLI.z & md, mn, \#i$^{ }_{6}$ & md$^{ }_{z*[z-1:i]}$ = mn$^{ }_{z*[z-i-1:0]}$ & \\ % z = 8,16,32,64
V\{R\}SRA.sz & md, mn, \#i$^{ }_{6}$ & md$^{ }_{z*}$ $+$= mn$^{ }_{z*}$ $\lsr^{s \{R\}}_{ }$ i & \\ % z = 8,16,32,64
VSRI.z & md, mn, \#i$^{ }_{6}$ & md$^{ }_{z*[z-i-1:0]}$ = mn$^{ }_{z*[z-1:i]}$ & \\ % z = 8,16,32,64
\end{asmtable5}
%
\begin{asmtable5}{SIMD Convertion Instructions}
VCVT.F16.F32 & Dd, Qn & Dd$^{ }_{16*}$ = Float2Float(Qn$^{ }_{32*}$) & SH \\
VCVT.F32.F16 & Qd, Dn & Qd$^{ }_{32*}$ = Float2Float(Dn$^{ }_{16*}$) & SH \\
VCVT.F32.s32 & md, mn & md$^{ }_{32*}$ = Int2Float(mn$^{s}_{32*}$) & \\
VCVT.F32.s32 & md, mn, \#i$^{ }_{6}$ & md$^{ }_{32*}$ = Fixed2Float(mn$^{s}_{32*}$, i) & \\
VCVT.s32.F32 & md, mn & md$^{ }_{32*}$ = Float2Int(mn)$^{s}_{32*}$ & \\
VCVT.s32.F32 & md, mn, \#i$^{ }_{6}$ & md$^{ }_{32*}$ = Float2Fixed(mn$^{s}_{32*}$, i) & \\
VCVTr.s32.F32 & md, mn & md$^{ }_{32*}$ = Float2Int(mn$^{ }_{32*}$, r)$^{s}_{ }$ & 8,I \\
VMOVL.sz & Qd, Dn & Qd$^{ }_{2z*}$ = Dn$^{s}_{z*}$ & \\ % z = 8,16,32
VMOVN.Iz & Dd, Qn & Dd$^{ }_{0\text{.}5z*}$ = Qn$^{ }_{z*[0\text{.}5z-1:0]}$ & \\ % z = 16,32,64
VQMOVN.sz & Dd, Qn & Dd$^{ }_{0\text{.}5z*}$ = $\lfloor$Qn$^{ }_{z*}$$\rceil^{s0.5z}$ & \\ % z = 16,32,64
VQMOVUN.Sz & Dd, Qn & Dd$^{ }_{0\text{.}5z*}$ = $\lfloor$Qn$^{ }_{z*}$$\rceil^{U0.5z}$ & \\ % z = 16,32,64
VRINT\{r,Z\}.F32 & md, mn & md$^{ }_{32*}$ = Round2Int(mn$^{ }_{32*}$, \{r,Z\}) & 8,I \\
VRINTX.F32 & md, mn & md$^{ }_{32*}$ = Round2Int(mn$^{ }_{32*}$, FPSCR) & 8,I \\
\end{asmtable5}
%
\begin{asmtable7}{SIMD Comparision Instructions}
VACcm.F32 & md, mn, mm & md$^{ }_{32*}$= $\lvert$mn$^{ }_{32*}$$\rvert$ cm $\lvert$mm$^{ }_{32*}$$\rvert$ ? 1$^{ }_{32}$: 0$^{ }_{32}$ & \\
VCEQ.Iz & md, mn, mm & md$^{ }_{z*}$ = (mn$^{ }_{z*}$ $\eq$ mm$^{ }_{z*}$) ? 1$^{ }_{z}$ : 0$^{ }_{z}$ & F \\ % z = 8,16,32
VCEQ.Iz & md, mn, \#0 & md$^{ }_{z*}$ = (mn$^{ }_{z*}$ $\eq$ 0) ? 1$^{ }_{z}$ : 0$^{ }_{z}$ & F \\ % z = 8,16,32
VCcm.sz & md, mn, mm & md$^{ }_{z*}$ = (mn$^{ }_{z*}$ cm$^{s}_{ }$ mm$^{ }_{z*}$) ? 1$^{ }_{z}$ : 0$^{ }_{z}$ & F \\ % z = 8,16,32
VCcm.Sz & md, mn, \#0 & md$^{ }_{z*}$ = (mn$^{ }_{z*}$ $\bar{cm}$ 0) ? 1$^{ }_{z}$ : 0$^{ }_{z}$ & F \\ % z = 8,16,32
VMAX.sz & md, mn, mm & md$^{ }_{z*}$ = mn$^{ }_{z*}$ $\max^{s}_{ }$ mm$^{ }_{z*}$ & F \\ % z = 8,16,32
VMAXNM.sz & md, mn, mm & md$^{ }_{z*}$ = mn$^{ }_{z*}$ $\max^{s}_{ }$ mm$^{ }_{z*}$ & 8,F,I \\ % z = 16,32
VMIN.sz & md, mn, mm & md$^{ }_{z*}$ = mn$^{ }_{z*}$ $\min^{s}_{ }$ mm$^{ }_{z*}$ & F \\ % z = 8,16,32
VMINNM.sz & md, mn, mm & md$^{ }_{z*}$ = mn$^{ }_{z*}$ $\min^{s}_{ }$ mm$^{ }_{z*}$ & 8,F,I \\ % z = 16,32
VPMAX.sz & Dd, Dn, Dm & Dd$^{ }_{z*}$ = (Dm:Dn)$^{ }_{z2*}$ $\max^{s}_{ }$ (Dm:Dn)$^{ }_{z2*+1}$ & F \\ % z = 8,16,32
VPMIN.sz & Dd, Dn, Dm & Dd$^{ }_{z*}$ = (Dm:Dn)$^{ }_{z2*}$ $\min^{s}_{ }$ (Dm:Dn)$^{ }_{z2*+1}$ & F \\ % z = 8,16,32
VTST.z & md, mn, mm & md$^{ }_{z*}$ = (mn$^{ }_{z*}$\&mm$^{ }_{z*}$ $\ne$ 0) ? 1$^{ }_{z}$ : 0$^{ }_{z}$ & \\ % z = 8,16,32
\end{asmtable7}
%
\newpage
\begin{center}
{\Large\bfseries ARMv8-A \& ARMv7-R System}
\end{center}
%
\begin{table-llXr}{Current Program Status Register (CPSR)}
M & 0x0000001f & Processor operating mode & \\
T & 0x00000020 & Instruction set (JT: 00=ARM, 01=Thumb) & \\
F & 0x00000040 & FIQ exception masked & \\
I & 0x00000080 & IRQ exception masked & \\
A & 0x00000100 & Asynchronous abort masked & 6 \\
E & 0x00000200 & Big-endian operation & 6 \\
IT & 0x0600fc00 & IT state bits & 6t\\
GE\{3..0\} & 0x000f0000 & SIMD greater than or equal to & 6 \\
PAN & 0x00400000 & Disable privileged access at PL0 & 8{\tiny 1},A \\
J & 0x01000000 & Instr set (JT: 10=Jazelle, 11=ThumbEE) & 6 \\
Q & 0x08000000 & Cumulative saturation bit & \\
V & 0x10000000 & Overflow condition flag & \\
C & 0x20000000 & Carry condition flag & \\
Z & 0x40000000 & Zero condition flag & \\
N & 0x80000000 & Negative condition flag & \\
\end{table-llXr}
%
\begin{table-llXr}{Processor Operating Modes}
usr & 0x10 & User & \\
fiq & 0x11 & FIQ & \\
irq & 0x12 & IRQ & \\
svc & 0x13 & Supervisor & \\
mon & 0x16 & Monitor (Secure only) & S\\
abt & 0x17 & Abort & \\
hyp & 0x1a & Hypervisor (Non-secure only) & V \\
und & 0x1b & Undefined & \\
sys & 0x1f & System & \\
\end{table-llXr}
%
\begin{table-lX}{Vectors}
0x00 & Reset \\
0x04 & Undefined instruction \\
0x08 & Supervisor call / Secure monitor call / Hypervisor call \\
0x0c & Prefetch abort \\
0x10 & Data abort \\
0x14 & Hyp trap \\
0x18 & IRQ interrupt \\
0x1c & FIQ interrupt \\
\end{table-lX}
%
\begin{table-lX}{Notes for System Registers and Tables}
6,6k,6t,7 & Introduced in ARMv6, ARMv6k, ARMv6T2, or ARMv7 \\
8,8{\tiny 1},8{\tiny 2} & Introduced in ARMv8, ARMv8.1, or ARMv8.2 \\
%\sout{7} & Removed in ARMv7 \\
A,R & Only present on ARM-A, or ARM-R \\
B & Banked between secure and non-secure usage \\
S & Only present with security extensions (Implies 6k,A) \\
V & Only present with virtualization extensions (Implies 7,A) \\
\end{table-lX}
%
\begin{table-llXr}{System Control Register (SCTLR)}
M & 0x00000001 & MMU enabled & B \\
A & 0x00000002 & Alignment check enabled & B \\
C & 0x00000004 & Data and unified caches enabled & B \\
%W & 0x00000008 & Write buffer enabled & \sout{7} \\
nTLSMD & 0x00000008 & Don't trap load/store multiple to device & 8{\tiny 2},A \\
LSMAOE & 0x00000010 & Don't interrupt load/store multiple & 8{\tiny 2},A \\
CP15BEN & 0x00000020 & CP15 barrier enable & 7,B \\
%B & 0x00000080 & Legacy big endian BE-32 format & \sout{7} \\
ITD & 0x00000080 & Disable deprecated IT usage at PL1 and PL0 & 8 \\
%S & 0x00000100 & System protection & \sout{7} \\
SED & 0x00000100 & Disable SETEND instructions & 8 \\
%R & 0x00000200 & ROM protection & \sout{7} \\
SW & 0x00000400 & Enable SWP and SWPB instructions & 6,B \\
Z & 0x00000800 & Program flow prediction enabled & B \\
I & 0x00001000 & Instruction cache enabled & B \\
V & 0x00002000 & High exception vectors & B \\
RR & 0x00004000 & Round robin select (Non-Secure RO) & \\
%L4 & 0x00008000 & Inhibit thumb interworking & \sout{7} \\
nTWI & 0x00010000 & Don't trap WFI from PL0 to undefined mode & 8 \\
HA & 0x00020000 & Hardware access flag enable & B,S \\
BR & 0x00020000 & Background region enable & 7,R \\
nTWE & 0x00040000 & Don't trap WFE from PL0 to undefined mode & 8 \\
WXN & 0x00080000 & Write force to XN & V \\
DZ & 0x00080000 & Divide by zero causes undefined instruction & 7,R \\
UWXN & 0x00100000 & Unprivileged write forced to XN for PL1 & V \\
FI & 0x00200000 & Fast interrupts (Non-Secure RO) & 6 \\
%U & 0x00400000 & Unaligned access support & 6,\sout{7} \\
%XP & 0x00800000 & Select virtual memory support model & 6,\sout{7} \\
PAN & 0x00800000 & Don't set CPSR.PAN on exception to PL1 & 8{\tiny 1},A \\
VE & 0x01000000 & Interrupt vectors enable & 6,B \\
EE & 0x02000000 & Exception endianess & 6,B \\
%L2 & 0x04000000 & Level 2 cache support & 6,\sout{7} \\
NMFI & 0x08000000 & Non-maskable FIQ support (RO) & 6 \\
TRE & 0x10000000 & TEX remap functionality enabled & B,S \\
AFE & 0x20000000 & Access flag enable & B,S \\
TE & 0x40000000 & Thumb exception enable & 6t,B \\
IE & 0x80000000 & Big-endian byte order in instructions & 7,R \\
\end{table-llXr}
%
\begin{table-llXr}{Secure Configuration Register (SCR)}
NS & 0x0001 & System state is non-secure unless in monitor mode & \\
IRQ & 0x0002 & IRQs taken to monitor mode & \\
FIQ & 0x0004 & FIQs taken to monitor mode & \\
EA & 0x0008 & External aborts taken to monitor mode & \\
FW & 0x0010 & CPSR.F writeable in non-secure state & \\
AW & 0x0020 & CPSR.A writeable in non-secure state & \\
nET & 0x0040 & Disable early termination & \\
SCD & 0x0080 & Secure monitor call disable & V \\
HCE & 0x0100 & Hyp call enable & V \\
SIF & 0x0200 & Secure instruction fetch & V \\
TWI & 0x1000 & Trap WFI instruction to monitor mode & 8 \\
TWE & 0x2000 & Trap WFE instruction to monitor mode & 8 \\
TERR & 0x8000 & Trap ER* access to monitor mode & 8 \\
\end{table-llXr}
%
%\begin{table-llX}{Non-Secure Access Control Register (NSACR)}
%CP\{0..13\} & 1 $\lsl$ \{0..13\} & CP\{0..13\} can be accessed in non-secure state \\
%NSD32DIS & 0x00004000 & CPACR.D32DIS is fixed 1 in non-secure state \\
%NSASEDIS & 0x00008000 & CPACR.ASEDIS is fixed 1 in non-secure state \\
%RFR & 0x00080000 & Reserve FIQ mode for non-secure \\
%NSTRCDIS & 0x00100000 & Disable non-secure access to CP14 trace regs \\
%\end{table-llX}
%
%\begin{table-llX}{Coprocessor Access Control Register (CPACR)}
%CP\{0..13\} & 3$\lsl$(2$\umul$\{0..13\}) & CP\{0..13\} access (00=denied, 01=privileged mode only, 11=privileged or user mode) \\
%TRCDIS & 0x10000000 & Disable CP14 access to trace registers \\
%D32DIS & 0x40000000 & Disable use of D16-D31 registers \\
%ASEDIS & 0x80000000 & Disable advanced SIMD functionality \\
%\end{table-llX}
%
\begin{table-llXr}{CP15 System Control Registers}
SCTLR & c1,0,c0,0 & System Control & \\
ACTLR & c1,0,c0,1 & Auxiliary Control & 6,B \\
CPACR & c1,0,c0,2 & Coprocessor Access Control & 6 \\
ACTLR2 & c1,0,c0,3 & Auxiliary Control bits 32-63 & 8{\tiny 2},B \\
SCR & c1,0,c1,0 & Secure Configuration (Secure only) & S \\
SDER & c1,0,c1,1 & Secure Debug Enable (Secure only) & S \\
NSACR & c1,0,c1,2 & Non-Secure Access Control (Non-Secure RO) & S \\
VBAR & c12,0,c0,0 & Vector Base & A,B \\
MVBAR & c12,0,c0,1 & Monitor Vector Base Address (Secure only) & A,S \\
RMR & c12,0,c0,2 & Reset Management & 8,A \\
ISR & c12,0,c1,0 & Interrupt Status (RO) & \\
\end{table-llXr}
%
\begin{table-llXr}{CP15 Memory System Registers}
DFSR & c5,0,c0,0 & Data Fault Status & B \\
IFSR & c5,0,c0,1 & Instruction Fault Status & 6,B \\
ADFSR & c5,0,c1,0 & Auxiliary DFSR & 7,B \\
AIFSR & c5,0,c1,1 & Auxiliary IFSR & 7,B \\
DFAR & c6,0,c0,0 & Data Fault Address & B \\
IFAR & c6,0,c0,2 & Instruction Fault Address & 6,B \\
DRBAR & c6,0,c1,0 & Data Region Base Address & R \\
IRBAR & c6,0,c1,1 & Instruction Region Base Address & R \\
DRSR & c6,0,c1,2 & Data Region Size and Enable & R \\
IRSR & c6,0,c1,3 & Instruction Region Size and Enable & R \\
DRACR & c6,0,c1,4 & Data Region Access Control & R \\
IRACR & c6,0,c1,5 & Instruction Region Access Control & R \\
RGNR & c6,0,c2,0 & MPU Region Number & R \\
\end{table-llXr}
%
\begin{table-llXr}{CP15 Memory Protection and Control Registers (ARM-A only)}
TTBR\{0,1\} & c2,0,c0,\{0,1\} & Translation Table Base \{0,1\} & B \\
TTBCR & c2,0,c0,2 & Translation Table Base Control & 6,B \\
TTBCR2 & c2,0,c0,3 & Trans Table Base Control bits 32-63 & 8{\tiny 2},B \\
TTBR\{0,1\} & c2,\{0,1\} & Translation Table Base \{0,1\} (LPAE) & 7,B \\
DACR & c3,0,c0,0 & Domain Access Control & B \\
PRRR & c10,0,c2,0 & Primary Region Remap & 6,B \\
NMRR & c10,0,c2,1 & Normal Memory Remap & 6,B \\
MAIR\{0,1\} & c10,0,c2,\{0,1\} & Memory Attr Indirection \{0,1\} & 7 \\
AMAIR\{0,1\} & c10,0,c3,\{0,1\} & Aux Memory Attribute Indirection \{0,1\} & 7 \\
\end{table-llXr}
%
\begin{table-llXr}{CP15 Process, Context, and Thread ID Registers}
FCSEIDR & c13,0,c0,0 & FSCE PID & A,B \\
CONTEXIDR & c13,0,c0,1 & Context ID & 6,B \\
TPIDRURW & c13,0,c0,2 & User Read/Write Thread ID & 6,B \\
TPIDRURO & c13,0,c0,3 & User Read-only Thread ID & 6,B \\
TPIDRPRW & c13,0,c0,4 & PL1 only Thread ID & 6,B \\
\end{table-llXr}
%
\begin{table-llXr}{CP15 ID Registers (Read-Only)}
MIDR & c0,0,c0,0 & Main ID & \\
CTR & c0,0,c0,1 & Cache Type & \\
TCMTR & c0,0,c0,2 & TCM Type & \\
TLBTR & c0,0,c0,3 & TLB Type & A \\
MPUIR & c0,0,c0,4 & MPU Type & R \\
MPIDR & c0,0,c0,5 & Multiprocessor Affinity & \\
REVIDR & c0,0,c0,6 & Revision ID & \\
ID\_PFR\{0..1\} & c0,0,c1,\{0..1\} & Processor Features \{0..1\} & 6 \\
ID\_DFR0 & c0,0,c1,2 & Debug Feature 0 & 6 \\
ID\_AFR0 & c0,0,c1,3 & Auxiliary Feature 0 & 6 \\
ID\_MMFR\{0..3\} & c0,0,c1,\{4..7\} & Memory Model Feature \{0..3\} & 6 \\
ID\_ISAR\{0..5\} & c0,0,c2,\{0..5\} & Instruction Set Attribute \{0..5\} & 6 \\
ID\_MMFR4 & c0,0,c2,6 & Memory Model Feature 4 & 8 \\
CCSIDR & c0,1,c0,0 & Cache Size ID & 7 \\
CLIDR & c0,1,c0,1 & Cache Level ID & 7 \\
AIDR & c0,1,c0,7 & Auxiliary ID & 7 \\
CSSELR & c0,2,c0,0 & Cache Size Selection (RW) & 7,B \\
\end{table-llXr}
%
\begin{table-llXr}{CP15 Performance Monitor Registers}
PMCR & c9,0,c12,0 & PM Control & \\
PMCNTEN\{SET,CLR\} & c9,0,c12,\{1,2\} & PM Count Enab \{Set,Clr\} & \\
PMOVSR & c9,0,c12,3 & PM Overflow Flag Status & \\
PMSWINC & c9,0,c12,4 & PM Software Increment & \\
PMSELR & c9,0,c12,5 & PM Event Counter Select & \\
PMCEID\{0,1\} & c9,0,c12,\{6,7\} & PM Com Event Id \{0,1\} & \\
PMCCNTR & c9,0,c13,0 & PM Cycle Count & \\
PMXEVTYPER & c9,0,c13,1 & PM Event Type Select & \\
PMXEVCNTR & c9,0,c13,2 & PM Event Count & \\
PMUSERENR & c9,0,c14,0 & PM User Enable & \\
PMINTEN\{SET,CLR\} & c9,0,c14,\{1,2\} & PM Inter Enab \{Set,Clr\} & \\