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arc_startup.s : SR to AUX_DC_IVDC should wait on FS bit #124

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yaroslavsadin opened this issue Jun 19, 2019 · 0 comments
Open

arc_startup.s : SR to AUX_DC_IVDC should wait on FS bit #124

yaroslavsadin opened this issue Jun 19, 2019 · 0 comments
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@vonhust
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bug
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2019.12 Release

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@yaroslavsadin
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Issue Summary

  • Type: Bug
  • Category: Library
  • Priority: Medium
  • Release Version: All

Bug

Development Environment

  • HOST OS
    All

  • TOOLCHAIN
    All

  • BOARD
    N/A

  • ARC CORE
    All

Bug Description

arc_startup.s line 81-82, here data cache is invalidated by writing to AUX_DC_IVDC and it is immediately enabled by writing to AUX_DC_CTRL. But according to documentation you first should wait on FS bit in DC_CTRL.
@fbedard fbedard added the bug label Jun 19, 2019
@fbedard fbedard added this to the 2019.06 Release milestone Jun 19, 2019
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@vonhust vonhust

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@fbedard @vonhust @yaroslavsadin @YuguoWH