Constant values on both counter blocks

[C47D]

If the counterAsc and counterDes blocks are used on the user project without the constant blocks they use a default value that i left on the component implementation, in case of using the constant blocks the latter constants are used.

It is better left the implementation like this or change the constants inside the blocks or warn the user that no constants are used at the project level?

[Jesus89]

Neither iverilog nor yosys complain about not adding a verilog module parameter. It automatically uses its default value.
In Icestudio the value inside the constant is the default value for the project. For the code blocks, all their parameters are initialized to 0.
I think we left this standard behaviour for now. In the future we may evaluate if any warning message is necessary.