You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Create a new concept in order to define default configurations in an FPGA board, using a file rules.json in a board directory that contains rules for undefined pins or connections. E.g. All unconnected "clk" ports are connected to CLK pin, if LED0 is not connected it is set to 0.
These smart rules will simplify the design and the setup of the designs.
The text was updated successfully, but these errors were encountered:
Create a new concept in order to define default configurations in an FPGA board, using a file rules.json in a board directory that contains rules for undefined pins or connections. E.g. All unconnected "clk" ports are connected to CLK pin, if LED0 is not connected it is set to 0.
These smart rules will simplify the design and the setup of the designs.
The text was updated successfully, but these errors were encountered: