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The idea is to generate graphic blocks with upper pins to connect "Constant" blocks
For example,
Add a code block with parameters "N,B"
Connect two constant blocks with values 22 and 0 to the code block N and B connections.
Export the project as a block
Then all the code blocks are parsed and a "parameters" list generated and included in the block.iceb file.
"parameters": [ { "name": "N", "value: "22", "default": "22" }, { "name": "B", "value: "0", "default": "0" } ]
The block appears with the upper pins "N,B".
Add and connect two Constant blocks N and B and write the values 23, 1.
These new values are updated in the project.ice file ("parameters" list).
The verilog compiler adds the parameters into the corresponding modules.
modtype #( .N(23), .B(1)) modname (...)
The text was updated successfully, but these errors were encountered:
Done: 5300804
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Merge pull request FPGAwars#98 from Jesus89/develop
d01808b
Add install --version X. Detect board type on upload.
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The idea is to generate graphic blocks with upper pins to connect "Constant" blocks
For example,
Add a code block with parameters "N,B"
Connect two constant blocks with values 22 and 0 to the code block N and B connections.
Export the project as a block
Then all the code blocks are parsed and a "parameters" list generated and included in the block.iceb file.
The block appears with the upper pins "N,B".
Add and connect two Constant blocks N and B and write the values 23, 1.
These new values are updated in the project.ice file ("parameters" list).
The verilog compiler adds the parameters into the corresponding modules.
The text was updated successfully, but these errors were encountered: