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added hdmi device nodes from hdmi-branch
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@frank-w
frank-w committed Feb 7, 2018
1 parent f5b5b75 commit e62269e
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312 changes: 312 additions & 0 deletions arch/arm/boot/dts/mt7623.dtsi
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Expand Up @@ -21,6 +21,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/mt2701-resets.h>
#include <dt-bindings/memory/mt2701-larb-port.h>
#include <dt-bindings/thermal/thermal.h>
#include "skeleton64.dtsi"

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#interrupt-cells = <2>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;

hdmi_pin: htplg {
pins1 {
pinmux = <MT7623_PIN_123_HTPLG_FUNC_HTPLG>;
input-enable;
bias-pull-down;
};
};
};

syscfg_pctl_a: syscfg@10005000 {
Expand Down Expand Up @@ -276,6 +285,17 @@
clock-names = "system-clk", "rtc-clk";
};

smi_common: smi@1000c000 {
compatible = "mediatek,mt7623-smi-common",
"mediatek,mt2701-smi-common";
reg = <0 0x1000c000 0 0x1000>;
clocks = <&infracfg CLK_INFRA_SMI>,
<&mmsys CLK_MM_SMI_COMMON>,
<&infracfg CLK_INFRA_SMI>;
clock-names = "apb", "smi", "async";
power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
};

pwrap: pwrap@1000d000 {
compatible = "mediatek,mt7623-pwrap",
"mediatek,mt2701-pwrap";
Expand All @@ -289,6 +309,25 @@
clock-names = "spi", "wrap";
};

mipi_tx0: mipi-dphy@10010000 {
compatible = "mediatek,mt7623-mipi-tx",
"mediatek,mt2701-mipi-tx";
reg = <0 0x10010000 0 0x90>;
clocks = <&clk26m>;
clock-output-names = "mipi_tx0_pll";
#clock-cells = <0>;
#phy-cells = <0>;
status = "disabled";
};

cec: cec@10012000 {
compatible = "mediatek,mt7623-cec",
"mediatek,mt8173-cec";
reg = <0 0x10012000 0 0xbc>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_CEC>;
};

cir: cir@10013000 {
compatible = "mediatek,mt7623-cir";
reg = <0 0x10013000 0 0x1000>;
Expand All @@ -307,6 +346,17 @@
reg = <0 0x10200100 0 0x1c>;
};

iommu: mmsys_iommu@10205000 {
compatible = "mediatek,mt7623-m4u",
"mediatek,mt2701-m4u";
reg = <0 0x10205000 0 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_M4U>;
clock-names = "bclk";
mediatek,larbs = <&larb0 &larb1 &larb2>;
#iommu-cells = <1>;
};

efuse: efuse@10206000 {
compatible = "mediatek,mt7623-efuse",
"mediatek,mt8173-efuse";
Expand All @@ -326,6 +376,20 @@
#clock-cells = <1>;
};

hdmi_phy: hdmi-phy@10209100 {
compatible = "mediatek,mt7623-hdmi-phy",
"mediatek,mt2701-hdmi-phy";
reg = <0 0x10209100 0 0x24>;
clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
clock-names = "pll_ref";
clock-output-names = "hdmitx_dig_cts";
mediatek,ibias = <0xa>;
mediatek,ibias_up = <0x1c>;
#clock-cells = <0>;
#phy-cells = <0>;
status = "disabled";
};

rng: rng@1020f000 {
compatible = "mediatek,mt7623-rng";
reg = <0 0x1020f000 0 0x1000>;
Expand Down Expand Up @@ -472,6 +536,15 @@
status = "disabled";
};

hdmiddc0: i2c@11013000 {
compatible = "mediatek,mt7623-hdmi-ddc",
"mediatek,mt8173-hdmi-ddc";
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
reg = <0 0x11013000 0 0x1C>;
clocks = <&pericfg CLK_PERI_I2C3>;
clock-names = "ddc-i2c";
};

thermal: thermal@1100b000 {
#thermal-sensor-cells = <1>;
compatible = "mediatek,mt7623-thermal",
Expand Down Expand Up @@ -685,6 +758,245 @@
status = "disabled";
};

mali: mali@13040000 {
compatible = "arm,mali-450", "arm,mali-utgard";
reg = <0 0x13040000 0 0x30000>, <0 0x13000000 0 0x20>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "IRQGP", "IRQGPMMU",
"IRQPP0", "IRQPPMMU0",
"IRQPP1", "IRQPPMMU1",
"IRQPP2", "IRQPPMMU2",
"IRQPP";
larb=<&larb0>;
clocks = <&topckgen CLK_TOP_UNIVPLL_D3>,
<&topckgen CLK_TOP_MMPLL>,
<&topckgen CLK_TOP_MFG_SEL>;
clock-names = "intermediate",
"mfg_pll",
"mfg_sel";
power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;
operating-points = <
107250 1150000
214500 1150000
312000 1150000
416000 1150000
>;
};

display_components: dispsys@14000000 {
compatible = "mediatek,mt7623-display",
"mediatek,mt2701-display";
reg = <0 0x14000000 0 0x1000>;
power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
};

mmsys: syscon@14000000 {
compatible = "mediatek,mt7623-mmsys",
"mediatek,mt2701-mmsys",
"syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
};

ovl@14007000 {
compatible = "mediatek,mt7623-disp-ovl",
"mediatek,mt2701-disp-ovl";
reg = <0 0x14007000 0 0x1000>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_DISP_OVL>;
iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>;
mediatek,larb = <&larb0>;
};

disp_rdma0: rdma@14008000 {
compatible = "mediatek,mt7623-disp-rdma",
"mediatek,mt2701-disp-rdma";
reg = <0 0x14008000 0 0x1000>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_DISP_RDMA>;
iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>;
mediatek,larb = <&larb0>;
};

wdma@14009000 {
compatible = "mediatek,mt7623-disp-wdma",
"mediatek,mt2701-disp-wdma";
reg = <0 0x14009000 0 0x1000>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_DISP_WDMA>;
iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;
mediatek,larb = <&larb0>;
};

bls@1400a000 {
compatible = "mediatek,mt7623-disp-bls",
"mediatek,mt2701-disp-bls";
reg = <0 0x1400a000 0 0x1000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_DISP_BLS>;
port {
bls_out: endpoint {
remote-endpoint = <&dpi0_in>;
};
};
};

color@1400b000 {
compatible = "mediatek,mt7623-disp-color",
"mediatek,mt2701-disp-color";
reg = <0 0x1400b000 0 0x1000>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_DISP_COLOR>;
};

dsi0: dsi@1400c000 {
compatible = "mediatek,mt7623-dsi",
"mediatek,mt2701-dsi";
reg = <0 0x1400c000 0 0x1000>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_DSI_ENGINE>, <&mmsys CLK_MM_DSI_DIG>,
<&mipi_tx0>;
clock-names = "engine", "digital", "hs";
mediatek,syscon-dsi = <&mmsys 0x138>;
phys = <&mipi_tx0>;
phy-names = "dphy";
status = "disabled";
};

mutex: mutex@1400e000 {
compatible = "mediatek,mt7623-disp-mutex",
"mediatek,mt2701-disp-mutex";
reg = <0 0x1400e000 0 0x1000>;
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_MUTEX_32K>;
};

larb0: larb@14010000 {
compatible = "mediatek,mt7623-smi-larb",
"mediatek,mt2701-smi-larb";
reg = <0 0x14010000 0 0x1000>;
mediatek,smi = <&smi_common>;
mediatek,larb-id = <0>;
clocks = <&mmsys CLK_MM_SMI_LARB0>,
<&mmsys CLK_MM_SMI_LARB0>;
clock-names = "apb", "smi";
power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
};

disp_rdma1: rdma@14012000 {
compatible = "mediatek,mt7623-disp-rdma",
"mediatek,mt2701-disp-rdma";
reg = <0 0x14012000 0 0x1000>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>;
mediatek,larb = <&larb0>;
};

dpi0: dpi@14014000 {
compatible = "mediatek,mt7623-dpi",
"mediatek,mt2701-dpi";
reg = <0 0x14014000 0 0x1000>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_DPI1_DIGL>,
<&mmsys CLK_MM_DPI1_ENGINE>,
<&topckgen CLK_TOP_TVDPLL>;
clock-names = "pixel",
"engine",
"pll";
status = "disabled";
port {
dpi0_out: endpoint@0 {
remote-endpoint = <&hdmi0_in>;
};

dpi0_in: endpoint@1 {
remote-endpoint = <&bls_out>;
};
};
};

hdmi0: hdmi@14015000 {
compatible = "mediatek,mt7623-hdmi",
"mediatek,mt8173-hdmi";
reg = <0 0x14015000 0 0x400>;
clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
<&mmsys CLK_MM_HDMI_PLL>,
<&mmsys CLK_MM_HDMI_AUDIO>,
<&mmsys CLK_MM_HDMI_SPDIF>;
clock-names = "pixel", "pll", "bclk", "spdif";
pinctrl-names = "default";
pinctrl-0 = <&hdmi_pin>;
phys = <&hdmi_phy>;
phy-names = "hdmi";
mediatek,syscon-hdmi = <&mmsys 0x900>;
cec = <&cec>;
ddc-i2c-bus = <&hdmiddc0>;
assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
assigned-clock-parents = <&hdmi_phy>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;

port@0 {
reg = <0>;

hdmi0_in: endpoint {
remote-endpoint = <&dpi0_out>;
};
};
};
};

imgsys: syscon@15000000 {
compatible = "mediatek,mt7623-imgsys",
"mediatek,mt2701-imgsys",
"syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
};

larb2: larb@15001000 {
compatible = "mediatek,mt7623-smi-larb",
"mediatek,mt2701-smi-larb";
reg = <0 0x15001000 0 0x1000>;
mediatek,smi = <&smi_common>;
mediatek,larb-id = <2>;
clocks = <&imgsys CLK_IMG_SMI_COMM>,
<&imgsys CLK_IMG_SMI_COMM>;
clock-names = "apb", "smi";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
};

vdecsys: syscon@16000000 {
compatible = "mediatek,mt7623-vdecsys",
"mediatek,mt2701-vdecsys",
"syscon";
reg = <0 0x16000000 0 0x1000>;
#clock-cells = <1>;
};

larb1: larb@16010000 {
compatible = "mediatek,mt7623-smi-larb",
"mediatek,mt2701-smi-larb";
reg = <0 0x16010000 0 0x1000>;
mediatek,smi = <&smi_common>;
mediatek,larb-id = <1>;
clocks = <&vdecsys CLK_VDEC_CKGEN>,
<&vdecsys CLK_VDEC_LARB>;
clock-names = "apb", "smi";
power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
};

consys: consys@18070000 {
compatible = "mediatek,mt7623-consys";
reg = <0 0x18070000 0 0x0200>, /*CONN_MCU_CONFIG_BASE */
Expand Down

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