mt6625l: add changes outside driver dir

- without watchdog-changes because toprgu seems to be added with c254e10 ("watchdog: mtk_wdt: mt8183: Add reset controller) - mt6625l: watchdog: implement data for mt6589 - timekeeping32: reverting changes for wifi-driver - dts: mt7623: reorder btif - fix missing sched_setscheduler export - re-add get_ds()
frank-w · Nov 1, 2021 · f32d0db · f32d0db
1 parent 632856b
commit f32d0db
Show file tree

Hide file tree

Showing 9 changed files with 171 additions and 3 deletions.
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
@@ -285,6 +285,8 @@
 		compatible = "mediatek,mt7623-wdt",
 			     "mediatek,mt6589-wdt";
 		reg = <0 0x10007000 0 0x100>;
+		interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_FALLING>;
+		#reset-cells = <1>;
 	};
 
 	timer: timer@10008000 {
@@ -513,13 +515,27 @@
 			     "mediatek,mtk-btif";
 		reg = <0 0x1100c000 0 0x1000>;
 		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_LOW>;
-		clocks = <&pericfg CLK_PERI_BTIF>;
-		clock-names = "main";
+		clocks = <&pericfg CLK_PERI_BTIF>, <&pericfg CLK_PERI_AP_DMA>;
+		clock-names = "main", "apdmac";
 		reg-shift = <2>;
 		reg-io-width = <4>;
 		status = "disabled";
 	};
 
+	btif_rx: btif_rx@11000800 {
+		compatible = "mediatek,btif_rx";
+		reg = <0 0x11000800 0 0x80>;
+		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
+		status = "okay";
+	};
+
+	btif_tx: btif_tx@11000780 {
+		compatible = "mediatek,btif_tx";
+		reg = <0 0x11000780 0 0x80>;
+		interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
+		status = "okay";
+	};
+
 	nandc: nfi@1100d000 {
 		compatible = "mediatek,mt7623-nfc",
 			     "mediatek,mt2701-nfc";
@@ -743,6 +759,29 @@
 		#clock-cells = <1>;
 	};
 
+	consys: consys@18070000 {
+		compatible = "mediatek,mt7623-consys";
+		reg = <0 0x18070000 0 0x0200>,  /*CONN_MCU_CONFIG_BASE      */
+			<0 0x10001000 0 0x1600>;  /*TOPCKGEN_BASE             */
+		clocks = <&infracfg CLK_INFRA_CONNMCU>;
+		clock-names = "consysbus";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_CONN>;
+		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>,  /* BGF_EINT */
+					<GIC_SPI 163 IRQ_TYPE_LEVEL_LOW>;  /* WDT_EINT */
+		resets = <&watchdog MT2701_TOPRGU_CONN_MCU_RST>;
+		reset-names = "connsys";
+		status="disabled";
+	};
+
+	wifi:wifi@180f0000 {
+		compatible = "mediatek,mt7623-wifi",
+					"mediatek,wifi";
+		reg = <0 0x180f0000 0 0x005c>;
+		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&pericfg CLK_PERI_AP_DMA>;
+		clock-names = "wifi-dma";
+	};
+
 	hifsys: syscon@1a000000 {
 		compatible = "mediatek,mt7623-hifsys",
 			     "mediatek,mt2701-hifsys",

diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
@@ -104,6 +104,18 @@
 		};
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		consys-reserve-memory {
+			compatible = "mediatek,consys-reserve-memory";
+			no-map;
+			size = <0 0x100000>;
+			alignment = <0 0x100000>;
+		};
+	};
+
 	leds {
 		compatible = "gpio-leds";
 		pinctrl-names = "default";
@@ -344,6 +356,36 @@
 	};
 };
 
+&pio {
+	consys_pins_default: consys_pins_default {
+		adie {
+			pinmux = <MT7623_PIN_60_WB_RSTB_FUNC_WB_RSTB>,
+				<MT7623_PIN_61_GPIO61_FUNC_TEST_FD>,
+				<MT7623_PIN_62_GPIO62_FUNC_TEST_FC>,
+				<MT7623_PIN_63_WB_SCLK_FUNC_WB_SCLK>,
+				<MT7623_PIN_64_WB_SDATA_FUNC_WB_SDATA>,
+				<MT7623_PIN_65_WB_SEN_FUNC_WB_SEN>,
+				<MT7623_PIN_66_WB_CRTL0_FUNC_WB_CRTL0>,
+				<MT7623_PIN_67_WB_CRTL1_FUNC_WB_CRTL1>,
+				<MT7623_PIN_68_WB_CRTL2_FUNC_WB_CRTL2>,
+				<MT7623_PIN_69_WB_CRTL3_FUNC_WB_CRTL3>,
+				<MT7623_PIN_70_WB_CRTL4_FUNC_WB_CRTL4>,
+				<MT7623_PIN_71_WB_CRTL5_FUNC_WB_CRTL5>;
+				bias-disable;
+		};
+	};
+};
+&consys {
+	mediatek,pwrap-regmap = <&pwrap>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&consys_pins_default>;
+	vcn18-supply = <&mt6323_vcn18_reg>;
+	vcn28-supply = <&mt6323_vcn28_reg>;
+	vcn33_bt-supply = <&mt6323_vcn33_bt_reg>;
+	vcn33_wifi-supply = <&mt6323_vcn33_wifi_reg>;
+	status = "okay";
+};
+
 &pcie {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pcie_default>;

diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
@@ -52,6 +52,12 @@ static __always_inline void uaccess_restore(unsigned int flags)
 extern int __get_user_bad(void);
 extern int __put_user_bad(void);
 
+/*
+ * Note that this is actually 0x1,0000,0000
+ */
+#define KERNEL_DS	0x00000000
+#define get_ds()	(KERNEL_DS)
+
 #ifdef CONFIG_MMU
 
 /*

diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
@@ -2109,6 +2109,18 @@ static const struct of_device_id of_pwrap_match_tbl[] = {
 };
 MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);
 
+struct regmap *pwrap_node_to_regmap(struct device_node *np)
+{
+	struct platform_device *pdev;
+	struct pmic_wrapper *wrp;
+	pdev = of_find_device_by_node(np);
+	if (!pdev)
+		return ERR_PTR(-ENODEV);
+	wrp = platform_get_drvdata(pdev);
+	return wrp->regmap;
+}
+EXPORT_SYMBOL_GPL(pwrap_node_to_regmap);
+
 static int pwrap_probe(struct platform_device *pdev)
 {
 	int ret, irq;

diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
@@ -75,6 +75,10 @@ static const struct mtk_wdt_data mt2712_data = {
 	.toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM,
 };
 
+static const struct mtk_wdt_data mt6589_data = {
+	.toprgu_sw_rst_num = 15,
+};
+
 static const struct mtk_wdt_data mt8183_data = {
 	.toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
 };
@@ -410,7 +414,7 @@ static int mtk_wdt_resume(struct device *dev)
 
 static const struct of_device_id mtk_wdt_dt_ids[] = {
 	{ .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
-	{ .compatible = "mediatek,mt6589-wdt" },
+	{ .compatible = "mediatek,mt6589-wdt", .data = &mt6589_data },
 	{ .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
 	{ .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
 	{ .compatible = "mediatek,mt8195-wdt", .data = &mt8195_data },

diff --git a/include/net/genetlink.h b/include/net/genetlink.h
@@ -180,6 +180,50 @@ genl_dumpit_info(struct netlink_callback *cb)
 }
 
 int genl_register_family(struct genl_family *family);
+
+/**
+ * genl_register_family_with_ops - register a generic netlink family with ops
+ * @family: generic netlink family
+ * @ops: operations to be registered
+ * @n_ops: number of elements to register
+ *
+ * Registers the specified family and operations from the specified table.
+ * Only one family may be registered with the same family name or identifier.
+ *
+ * The family id may equal GENL_ID_GENERATE causing an unique id to
+ * be automatically generated and assigned.
+ *
+ * Either a doit or dumpit callback must be specified for every registered
+ * operation or the function will fail. Only one operation structure per
+ * command identifier may be registered.
+ *
+ * See include/net/genetlink.h for more documenation on the operations
+ * structure.
+ *
+ * Return 0 on success or a negative error code.
+ */
+static inline int
+_genl_register_family_with_ops_grps(struct genl_family *family,
+				    const struct genl_ops *ops, size_t n_ops,
+				    const struct genl_multicast_group *mcgrps,
+				    size_t n_mcgrps)
+{
+	family->module = THIS_MODULE;
+	family->ops = ops;
+	family->n_ops = n_ops;
+	family->mcgrps = mcgrps;
+	family->n_mcgrps = n_mcgrps;
+	return genl_register_family(family);
+}
+#define genl_register_family_with_ops(family, ops)			\
+	_genl_register_family_with_ops_grps((family),			\
+					    (ops), ARRAY_SIZE(ops),	\
+					    NULL, 0)
+#define genl_register_family_with_ops_groups(family, ops, grps)	\
+	_genl_register_family_with_ops_grps((family),			\
+					    (ops), ARRAY_SIZE(ops),	\
+					    (grps), ARRAY_SIZE(grps))
+
 int genl_unregister_family(const struct genl_family *family);
 void genl_notify(const struct genl_family *family, struct sk_buff *skb,
 		 struct genl_info *info, u32 group, gfp_t flags);

diff --git a/include/soc/mediatek/pmic_wrap.h b/include/soc/mediatek/pmic_wrap.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2015 MediaTek Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_MEDIATEK_PMIC_WRAP_H
+#define __SOC_MEDIATEK_PMIC_WRAP_H
+
+extern struct regmap *pwrap_node_to_regmap(struct device_node *np);
+
+#endif /* __SOC_MEDIATEK_PMIC_WRAP_H */
diff --git a/include/uapi/linux/genetlink.h b/include/uapi/linux/genetlink.h
@@ -27,6 +27,7 @@ struct genlmsghdr {
 /*
  * List of reserved static generic netlink identifiers:
  */
+#define GENL_ID_GENERATE	0
 #define GENL_ID_CTRL		NLMSG_MIN_TYPE
 #define GENL_ID_VFS_DQUOT	(NLMSG_MIN_TYPE + 1)
 #define GENL_ID_PMCRAID		(NLMSG_MIN_TYPE + 2)

diff --git a/kernel/sched/core.c b/kernel/sched/core.c
@@ -7513,6 +7513,7 @@ int sched_setscheduler(struct task_struct *p, int policy,
 {
 	return _sched_setscheduler(p, policy, param, true);
 }
+EXPORT_SYMBOL_GPL(sched_setscheduler);
 
 int sched_setattr(struct task_struct *p, const struct sched_attr *attr)
 {