openocd.cfg

#
# OpenOCD configuration file for LoRa-E5 Dev Board with a single STM32WLE5JC chip
#

source [find interface/stlink-dap.cfg]

# Shared access to debugger using stlink server
#st-link backend tcp

set WORKAREASIZE 0x8000

transport select "dapdirect_swd"

set CHIPNAME STM32WLE5JC

# Enable debug when in low power modes
set ENABLE_LOW_POWER 1

# Stop Watchdog counters when halt
set STOP_WATCHDOG 1

# STlink Debug clock frequency
set CLOCK_FREQ 8000

# Reset configuration
# use hardware reset, connect under reset
# connect_assert_srst needed if low power mode application running (WFI...)
reset_config srst_only srst_nogate connect_assert_srst
# See https://github.com/stm32-rs/stm32wlxx-hal/tree/main/lora-e5-bsp#flashing
set CONNECT_UNDER_RESET 1
set CORE_RESET 0

# ACCESS PORT NUMBER
set AP_NUM 0
# GDB PORT
set GDB_PORT 50000

#set DUAL_CORE 1

source [find target/stm32wlx.cfg]