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msm_serial_hs.c
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msm_serial_hs.c
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// SPDX-License-Identifier: GPL-2.0-only
/* drivers/serial/msm_serial_hs.c
*
* MSM 7k High speed uart driver
*
* Copyright (c) 2008 Google Inc.
* Copyright (c) 2007-2018, 2020, The Linux Foundation. All rights reserved.
* Modified: Nick Pelly <npelly@google.com>
*
* Has optional support for uart power management independent of linux
* suspend/resume:
*
* RX wakeup.
* UART wakeup can be triggered by RX activity (using a wakeup GPIO on the
* UART RX pin). This should only be used if there is not a wakeup
* GPIO on the UART CTS, and the first RX byte is known (for example, with the
* Bluetooth Texas Instruments HCILL protocol), since the first RX byte will
* always be lost. RTS will be asserted even while the UART is off in this mode
* of operation. See msm_serial_hs_platform_data.rx_wakeup_irq.
*/
#include <linux/module.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/atomic.h>
#include <linux/kernel.h>
#include <linux/timer.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/dma-mapping.h>
#include <linux/tty_flip.h>
#include <linux/wait.h>
#include <linux/sysfs.h>
#include <linux/stat.h>
#include <linux/device.h>
#include <linux/debugfs.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/gpio.h>
#include <linux/ipc_logging.h>
#include <asm/irq.h>
#include <linux/kthread.h>
#include <linux/msm-sps.h>
#include <linux/platform_data/msm_serial_hs.h>
#include <linux/interconnect.h>
#include "msm_serial_hs_hwreg.h"
#define UART_SPS_CONS_PERIPHERAL 0
#define UART_SPS_PROD_PERIPHERAL 1
#define IPC_MSM_HS_LOG_STATE_PAGES 2
#define IPC_MSM_HS_LOG_USER_PAGES 2
#define IPC_MSM_HS_LOG_DATA_PAGES 3
#define UART_DMA_DESC_NR 8
#define BUF_DUMP_SIZE 32
/* If the debug_mask gets set to FATAL_LEV,
* a fatal error has happened and further IPC logging
* is disabled so that this problem can be detected
*/
enum {
FATAL_LEV = 0U,
ERR_LEV = 1U,
WARN_LEV = 2U,
INFO_LEV = 3U,
DBG_LEV = 4U,
};
#define MSM_HS_DBG(x...) do { \
if (msm_uport->ipc_debug_mask >= DBG_LEV) { \
ipc_log_string(msm_uport->ipc_msm_hs_log_ctxt, x); \
} \
} while (0)
#define MSM_HS_INFO(x...) do { \
if (msm_uport->ipc_debug_mask >= INFO_LEV) {\
ipc_log_string(msm_uport->ipc_msm_hs_log_ctxt, x); \
} \
} while (0)
/* warnings and errors show up on console always */
#define MSM_HS_WARN(x...) do { \
pr_warn(x); \
if (msm_uport->ipc_msm_hs_log_ctxt && \
msm_uport->ipc_debug_mask >= WARN_LEV) \
ipc_log_string(msm_uport->ipc_msm_hs_log_ctxt, x); \
} while (0)
/* ERROR condition in the driver sets the hs_serial_debug_mask
* to ERR_FATAL level, so that this message can be seen
* in IPC logging. Further errors continue to log on the console
*/
#define MSM_HS_ERR(x...) do { \
pr_err(x); \
if (msm_uport->ipc_msm_hs_log_ctxt && \
msm_uport->ipc_debug_mask >= ERR_LEV) { \
ipc_log_string(msm_uport->ipc_msm_hs_log_ctxt, x); \
msm_uport->ipc_debug_mask = FATAL_LEV; \
} \
} while (0)
#define LOG_USR_MSG(ctx, x...) ipc_log_string(ctx, x)
/*
* There are 3 different kind of UART Core available on MSM.
* High Speed UART (i.e. Legacy HSUART), GSBI based HSUART
* and BSLP based HSUART.
*/
enum uart_core_type {
LEGACY_HSUART,
GSBI_HSUART,
BLSP_HSUART,
};
enum flush_reason {
FLUSH_NONE,
FLUSH_DATA_READY,
FLUSH_DATA_INVALID, /* values after this indicate invalid data */
FLUSH_IGNORE,
FLUSH_STOP,
FLUSH_SHUTDOWN,
};
/*
* SPS data structures to support HSUART with BAM
* @sps_pipe - This struct defines BAM pipe descriptor
* @sps_connect - This struct defines a connection's end point
* @sps_register - This struct defines a event registration parameters
*/
struct msm_hs_sps_ep_conn_data {
struct sps_pipe *pipe_handle;
struct sps_connect config;
struct sps_register_event event;
};
struct msm_hs_tx {
bool dma_in_flight; /* tx dma in progress */
enum flush_reason flush;
wait_queue_head_t wait;
int tx_count;
dma_addr_t dma_base;
struct kthread_work kwork;
struct kthread_worker kworker;
struct task_struct *task;
struct msm_hs_sps_ep_conn_data cons;
struct timer_list tx_timeout_timer;
void *ipc_tx_ctxt;
};
struct msm_hs_rx {
enum flush_reason flush;
wait_queue_head_t wait;
dma_addr_t rbuffer;
unsigned char *buffer;
unsigned int buffer_pending;
struct delayed_work flip_insert_work;
struct kthread_work kwork;
struct kthread_worker kworker;
struct task_struct *task;
struct msm_hs_sps_ep_conn_data prod;
unsigned long queued_flag;
unsigned long pending_flag;
int rx_inx;
struct sps_iovec iovec[UART_DMA_DESC_NR]; /* track descriptors */
void *ipc_rx_ctxt;
};
enum buffer_states {
NONE_PENDING = 0x0,
FIFO_OVERRUN = 0x1,
PARITY_ERROR = 0x2,
CHARS_NORMAL = 0x4,
};
enum msm_hs_pm_state {
MSM_HS_PM_ACTIVE,
MSM_HS_PM_SUSPENDED,
MSM_HS_PM_SYS_SUSPENDED,
};
/* optional low power wakeup, typically on a GPIO RX irq */
struct msm_hs_wakeup {
int irq; /* < 0 indicates low power wakeup disabled */
unsigned char ignore; /* bool */
/* bool: inject char into rx tty on wakeup */
bool inject_rx;
unsigned char rx_to_inject;
bool enabled;
bool freed;
};
struct msm_hs_port {
struct uart_port uport;
unsigned long imr_reg; /* shadow value of UARTDM_IMR */
struct clk *clk;
struct clk *pclk;
struct msm_hs_tx tx;
struct msm_hs_rx rx;
atomic_t resource_count;
struct msm_hs_wakeup wakeup;
struct dentry *loopback_dir;
struct work_struct clock_off_w; /* work for actual clock off */
struct workqueue_struct *hsuart_wq; /* hsuart workqueue */
struct mutex mtx; /* resource access mutex */
enum uart_core_type uart_type;
unsigned long bam_handle;
resource_size_t bam_mem;
int bam_irq;
unsigned char __iomem *bam_base;
unsigned int bam_tx_ep_pipe_index;
unsigned int bam_rx_ep_pipe_index;
/* struct sps_event_notify is an argument passed when triggering a
* callback event object registered for an SPS connection end point.
*/
struct sps_event_notify notify;
/* bus client handler */
u32 bus_perf_client;
/* BLSP UART required ICC BUS voting */
struct icc_path *icc_path;
bool rx_bam_inprogress;
wait_queue_head_t bam_disconnect_wait;
bool use_pinctrl;
struct pinctrl *pinctrl;
struct pinctrl_state *gpio_state_active;
struct pinctrl_state *gpio_state_suspend;
bool flow_control;
enum msm_hs_pm_state pm_state;
atomic_t client_count;
bool obs; /* out of band sleep flag */
atomic_t client_req_state;
void *ipc_msm_hs_log_ctxt;
void *ipc_msm_hs_pwr_ctxt;
int ipc_debug_mask;
};
static const struct of_device_id msm_hs_match_table[] = {
{ .compatible = "qcom,msm-hsuart-v14"},
{}
};
#define MSM_UARTDM_BURST_SIZE 16 /* DM burst size (in bytes) */
#define UARTDM_TX_BUF_SIZE UART_XMIT_SIZE
#define UARTDM_RX_BUF_SIZE 512
#define RETRY_TIMEOUT 5
#define UARTDM_NR 256
#define BAM_PIPE_MIN 0
#define BAM_PIPE_MAX 11
#define BUS_SCALING 1
#define BUS_RESET 0
#define RX_FLUSH_COMPLETE_TIMEOUT 300 /* In jiffies */
#define BLSP_UART_CLK_FMAX 63160000
/* Interconnect path bandwidths (each times 1000 bytes per second) */
#define BLSP_MEMORY_AVG 500
#define BLSP_MEMORY_PEAK 800
static struct dentry *debug_base;
static struct platform_driver msm_serial_hs_platform_driver;
static struct uart_driver msm_hs_driver;
static const struct uart_ops msm_hs_ops;
static void msm_hs_start_rx_locked(struct uart_port *uport);
static void msm_serial_hs_rx_work(struct kthread_work *work);
static void flip_insert_work(struct work_struct *work);
static struct msm_hs_port *msm_hs_get_hs_port(int port_index);
static void msm_hs_queue_rx_desc(struct msm_hs_port *msm_uport);
static int disconnect_rx_endpoint(struct msm_hs_port *msm_uport);
static int msm_hs_pm_resume(struct device *dev);
#define UARTDM_TO_MSM(uart_port) \
container_of((uart_port), struct msm_hs_port, uport)
static int msm_hs_ioctl(struct uart_port *uport, unsigned int cmd,
unsigned long arg)
{
int ret = 0, state = 1;
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
if (!msm_uport)
return -ENODEV;
switch (cmd) {
case MSM_ENABLE_UART_CLOCK: {
ret = msm_hs_request_clock_on(&msm_uport->uport);
break;
}
case MSM_DISABLE_UART_CLOCK: {
ret = msm_hs_request_clock_off(&msm_uport->uport);
break;
}
case MSM_GET_UART_CLOCK_STATUS: {
/* Return value 0 - UART CLOCK is OFF
* Return value 1 - UART CLOCK is ON
*/
if (msm_uport->pm_state != MSM_HS_PM_ACTIVE)
state = 0;
ret = state;
MSM_HS_INFO("%s():GET UART CLOCK STATUS: cmd=%d state=%d\n",
__func__, cmd, state);
break;
}
default: {
MSM_HS_INFO("%s():Unknown cmd specified: cmd=%d\n", __func__,
cmd);
ret = -ENOIOCTLCMD;
break;
}
}
return ret;
}
/*
* This function is called initially during probe and then
* through the runtime PM framework. The function directly calls
* resource APIs to enable them.
*/
static int msm_hs_clk_bus_vote(struct msm_hs_port *msm_uport)
{
int rc = 0;
int ret;
if (msm_uport->icc_path)
ret = icc_set_bw(msm_uport->icc_path,
BLSP_MEMORY_AVG, BLSP_MEMORY_PEAK);
/* Turn on core clk and iface clk */
if (msm_uport->pclk) {
rc = clk_prepare_enable(msm_uport->pclk);
if (rc) {
dev_err(msm_uport->uport.dev,
"%s(): Could not turn on pclk [%d]\n",
__func__, rc);
goto busreset;
}
}
rc = clk_prepare_enable(msm_uport->clk);
if (rc) {
dev_err(msm_uport->uport.dev,
"%s(): Could not turn on core clk [%d]\n",
__func__, rc);
goto core_unprepare;
}
MSM_HS_DBG("%s(): Clock ON successful\n", __func__);
return rc;
core_unprepare:
clk_disable_unprepare(msm_uport->pclk);
busreset:
if (msm_uport->icc_path)
ret = icc_set_bw(msm_uport->icc_path, 0, 0);
return rc;
}
/*
* This function is called initially during probe and then
* through the runtime PM framework. The function directly calls
* resource apis to disable them.
*/
static void msm_hs_clk_bus_unvote(struct msm_hs_port *msm_uport)
{
int ret;
clk_disable_unprepare(msm_uport->clk);
if (msm_uport->pclk)
clk_disable_unprepare(msm_uport->pclk);
if (msm_uport->icc_path)
ret = icc_set_bw(msm_uport->icc_path, 0, 0);
MSM_HS_DBG("%s(): Clock OFF successful\n", __func__);
}
/* Remove vote for resources when done */
static void msm_hs_resource_unvote(struct msm_hs_port *msm_uport)
{
struct uart_port *uport = &(msm_uport->uport);
int rc = atomic_read(&msm_uport->resource_count);
MSM_HS_DBG("%s(): power usage count %d\n", __func__, rc);
if (rc <= 0) {
MSM_HS_WARN("%s(): rc zero, bailing\n", __func__);
WARN_ON(1);
return;
}
atomic_dec(&msm_uport->resource_count);
pm_runtime_mark_last_busy(uport->dev);
pm_runtime_put_autosuspend(uport->dev);
}
/* Vote for resources before accessing them */
static void msm_hs_resource_vote(struct msm_hs_port *msm_uport)
{
int ret;
struct uart_port *uport = &(msm_uport->uport);
ret = pm_runtime_get_sync(uport->dev);
if (ret < 0 || msm_uport->pm_state != MSM_HS_PM_ACTIVE) {
MSM_HS_WARN("%s():%s runtime PM CB not invoked ret:%d st:%d\n",
__func__, dev_name(uport->dev), ret,
msm_uport->pm_state);
msm_hs_pm_resume(uport->dev);
}
atomic_inc(&msm_uport->resource_count);
}
/* Check if the uport line number matches with user id stored in pdata.
* User id information is stored during initialization. This function
* ensues that the same device is selected
*/
static struct msm_hs_port *get_matching_hs_port(struct platform_device *pdev)
{
struct msm_serial_hs_platform_data *pdata = pdev->dev.platform_data;
struct msm_hs_port *msm_uport = msm_hs_get_hs_port(pdev->id);
if ((!msm_uport) || (msm_uport->uport.line != pdev->id
&& msm_uport->uport.line != pdata->userid)) {
pr_err("uport line number mismatch\n");
WARN_ON(1);
return NULL;
}
return msm_uport;
}
static ssize_t clock_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
int state = 1;
ssize_t ret = 0;
struct platform_device *pdev = container_of(dev, struct
platform_device, dev);
struct msm_hs_port *msm_uport = get_matching_hs_port(pdev);
/* This check should not fail */
if (msm_uport) {
if (msm_uport->pm_state != MSM_HS_PM_ACTIVE)
state = 0;
ret = scnprintf(buf, PAGE_SIZE, "%d\n", state);
}
return ret;
}
static ssize_t clock_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
int state;
ssize_t ret = 0;
struct platform_device *pdev = container_of(dev, struct
platform_device, dev);
struct msm_hs_port *msm_uport = get_matching_hs_port(pdev);
/* This check should not fail */
if (msm_uport) {
state = buf[0] - '0';
switch (state) {
case 0:
MSM_HS_DBG("%s(): Request clock OFF\n", __func__);
msm_hs_request_clock_off(&msm_uport->uport);
ret = count;
break;
case 1:
MSM_HS_DBG("%s(): Request clock ON\n", __func__);
msm_hs_request_clock_on(&msm_uport->uport);
ret = count;
break;
default:
ret = -EINVAL;
}
}
return ret;
}
static DEVICE_ATTR_RW(clock);
static ssize_t debug_mask_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
ssize_t ret = 0;
struct platform_device *pdev = container_of(dev, struct
platform_device, dev);
struct msm_hs_port *msm_uport = get_matching_hs_port(pdev);
/* This check should not fail */
if (msm_uport)
ret = scnprintf(buf, sizeof(int), "%u\n",
msm_uport->ipc_debug_mask);
return ret;
}
static ssize_t debug_mask_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct platform_device *pdev = container_of(dev, struct
platform_device, dev);
struct msm_hs_port *msm_uport = get_matching_hs_port(pdev);
/* This check should not fail */
if (msm_uport) {
msm_uport->ipc_debug_mask = buf[0] - '0';
if (msm_uport->ipc_debug_mask < FATAL_LEV ||
msm_uport->ipc_debug_mask > DBG_LEV) {
/* set to default level */
msm_uport->ipc_debug_mask = INFO_LEV;
MSM_HS_ERR("Range is 0 to 4;Set to default level 3\n");
return -EINVAL;
}
}
return count;
}
static DEVICE_ATTR_RW(debug_mask);
static inline bool is_use_low_power_wakeup(struct msm_hs_port *msm_uport)
{
return msm_uport->wakeup.irq > 0;
}
static inline unsigned int msm_hs_read(struct uart_port *uport,
unsigned int index)
{
return readl_relaxed(uport->membase + index);
}
static inline void msm_hs_write(struct uart_port *uport, unsigned int index,
unsigned int value)
{
writel_relaxed(value, uport->membase + index);
}
static int sps_rx_disconnect(struct sps_pipe *sps_pipe_handler)
{
struct sps_connect config;
int ret;
ret = sps_get_config(sps_pipe_handler, &config);
if (ret) {
pr_err("%s(): sps_get_config() failed ret %d\n", __func__, ret);
return ret;
}
config.options |= SPS_O_POLL;
ret = sps_set_config(sps_pipe_handler, &config);
if (ret) {
pr_err("%s(): sps_set_config() failed ret %d\n", __func__, ret);
return ret;
}
return sps_disconnect(sps_pipe_handler);
}
static void hex_dump_ipc(struct msm_hs_port *msm_uport, void *ipc_ctx,
char *prefix, char *string, u64 addr, int size)
{
char buf[(BUF_DUMP_SIZE * 3) + 2];
int len = 0;
len = min(size, BUF_DUMP_SIZE);
/*
* Print upto 32 data bytes, 32 bytes per line, 1 byte at a time and
* don't include the ASCII text at the end of the buffer.
*/
hex_dump_to_buffer(string, len, 32, 1, buf, sizeof(buf), false);
ipc_log_string(ipc_ctx, "%s[0x%.10x:%d] : %s", prefix,
(unsigned int)addr, size, buf);
}
/*
* This API read and provides UART Core registers information.
*/
static void dump_uart_hs_registers(struct msm_hs_port *msm_uport)
{
struct uart_port *uport = &(msm_uport->uport);
if (msm_uport->pm_state != MSM_HS_PM_ACTIVE) {
MSM_HS_INFO("%s():Failed clocks are off, resource_count %d\n",
__func__, atomic_read(&msm_uport->resource_count));
return;
}
MSM_HS_DBG(
"MR1:%x MR2:%x TFWR:%x RFWR:%x DMEN:%x IMR:%x MISR:%x NCF_TX:%x\n",
msm_hs_read(uport, UART_DM_MR1),
msm_hs_read(uport, UART_DM_MR2),
msm_hs_read(uport, UART_DM_TFWR),
msm_hs_read(uport, UART_DM_RFWR),
msm_hs_read(uport, UART_DM_DMEN),
msm_hs_read(uport, UART_DM_IMR),
msm_hs_read(uport, UART_DM_MISR),
msm_hs_read(uport, UART_DM_NCF_TX));
MSM_HS_INFO("SR:%x ISR:%x DMRX:%x RX_SNAP:%x TXFS:%x RXFS:%x\n",
msm_hs_read(uport, UART_DM_SR),
msm_hs_read(uport, UART_DM_ISR),
msm_hs_read(uport, UART_DM_DMRX),
msm_hs_read(uport, UART_DM_RX_TOTAL_SNAP),
msm_hs_read(uport, UART_DM_TXFS),
msm_hs_read(uport, UART_DM_RXFS));
MSM_HS_DBG("rx.flush:%u\n", msm_uport->rx.flush);
}
static int msm_serial_loopback_enable_set(void *data, u64 val)
{
struct msm_hs_port *msm_uport = data;
struct uart_port *uport = &(msm_uport->uport);
unsigned long flags;
int ret = 0;
msm_hs_resource_vote(msm_uport);
if (val) {
spin_lock_irqsave(&uport->lock, flags);
ret = msm_hs_read(uport, UART_DM_MR2);
ret |= (UARTDM_MR2_LOOP_MODE_BMSK |
UARTDM_MR2_RFR_CTS_LOOP_MODE_BMSK);
msm_hs_write(uport, UART_DM_MR2, ret);
spin_unlock_irqrestore(&uport->lock, flags);
} else {
spin_lock_irqsave(&uport->lock, flags);
ret = msm_hs_read(uport, UART_DM_MR2);
ret &= ~(UARTDM_MR2_LOOP_MODE_BMSK |
UARTDM_MR2_RFR_CTS_LOOP_MODE_BMSK);
msm_hs_write(uport, UART_DM_MR2, ret);
spin_unlock_irqrestore(&uport->lock, flags);
}
/* Calling CLOCK API. Hence mb() requires here. */
mb();
msm_hs_resource_unvote(msm_uport);
return 0;
}
static int msm_serial_loopback_enable_get(void *data, u64 *val)
{
struct msm_hs_port *msm_uport = data;
struct uart_port *uport = &(msm_uport->uport);
unsigned long flags;
int ret = 0;
msm_hs_resource_vote(msm_uport);
spin_lock_irqsave(&uport->lock, flags);
ret = msm_hs_read(&msm_uport->uport, UART_DM_MR2);
spin_unlock_irqrestore(&uport->lock, flags);
msm_hs_resource_unvote(msm_uport);
*val = (ret & UARTDM_MR2_LOOP_MODE_BMSK) ? 1 : 0;
return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(loopback_enable_fops, msm_serial_loopback_enable_get,
msm_serial_loopback_enable_set, "%llu\n");
/*
* msm_serial_hs debugfs node: <debugfs_root>/msm_serial_hs/loopback.<id>
* writing 1 turns on internal loopback mode in HW. Useful for automation
* test scripts.
* writing 0 disables the internal loopback mode. Default is disabled.
*/
static void msm_serial_debugfs_init(struct msm_hs_port *msm_uport,
int id)
{
char node_name[15];
scnprintf(node_name, sizeof(node_name), "loopback.%d", id);
msm_uport->loopback_dir = debugfs_create_file(node_name,
0644,
debug_base,
msm_uport,
&loopback_enable_fops);
if (IS_ERR_OR_NULL(msm_uport->loopback_dir))
MSM_HS_ERR("%s(): Cannot create loopback.%d debug entry\n",
__func__, id);
}
static int msm_hs_remove(struct platform_device *pdev)
{
struct msm_hs_port *msm_uport;
struct device *dev;
if (pdev->id < 0 || pdev->id >= UARTDM_NR) {
pr_err("Invalid plaform device ID = %d\n", pdev->id);
return -EINVAL;
}
msm_uport = get_matching_hs_port(pdev);
if (!msm_uport)
return -EINVAL;
dev = msm_uport->uport.dev;
sysfs_remove_file(&pdev->dev.kobj, &dev_attr_clock.attr);
sysfs_remove_file(&pdev->dev.kobj, &dev_attr_debug_mask.attr);
debugfs_remove(msm_uport->loopback_dir);
dma_free_coherent(msm_uport->uport.dev,
UART_DMA_DESC_NR * UARTDM_RX_BUF_SIZE,
msm_uport->rx.buffer, msm_uport->rx.rbuffer);
msm_uport->rx.buffer = NULL;
msm_uport->rx.rbuffer = 0;
destroy_workqueue(msm_uport->hsuart_wq);
mutex_destroy(&msm_uport->mtx);
uart_remove_one_port(&msm_hs_driver, &msm_uport->uport);
clk_put(msm_uport->clk);
if (msm_uport->pclk)
clk_put(msm_uport->pclk);
iounmap(msm_uport->uport.membase);
return 0;
}
/* Connect a UART peripheral's SPS endpoint(consumer endpoint)
*
* Also registers a SPS callback function for the consumer
* process with the SPS driver
*
* @uport - Pointer to uart uport structure
*
* @return - 0 if successful else negative value.
*
*/
static int msm_hs_spsconnect_tx(struct msm_hs_port *msm_uport)
{
int ret;
struct uart_port *uport = &msm_uport->uport;
struct msm_hs_tx *tx = &msm_uport->tx;
struct sps_pipe *sps_pipe_handle = tx->cons.pipe_handle;
struct sps_connect *sps_config = &tx->cons.config;
struct sps_register_event *sps_event = &tx->cons.event;
unsigned long flags;
unsigned int data;
if (tx->flush != FLUSH_SHUTDOWN) {
MSM_HS_ERR("%s():Invalid flush state:%d\n",
__func__, tx->flush);
return 0;
}
/* Establish connection between peripheral and memory endpoint */
ret = sps_connect(sps_pipe_handle, sps_config);
if (ret) {
MSM_HS_ERR("msm_serial_hs: sps_connect() failed for tx\n"
"pipe_handle=0x%pK ret=%d", sps_pipe_handle, ret);
return ret;
}
/* Register callback event for EOT (End of transfer) event. */
ret = sps_register_event(sps_pipe_handle, sps_event);
if (ret) {
MSM_HS_ERR("msm_serial_hs: sps_connect() failed for tx\n"
"pipe_handle=0x%pK ret=%d", sps_pipe_handle, ret);
goto reg_event_err;
}
spin_lock_irqsave(&(msm_uport->uport.lock), flags);
msm_uport->tx.flush = FLUSH_STOP;
spin_unlock_irqrestore(&(msm_uport->uport.lock), flags);
data = msm_hs_read(uport, UART_DM_DMEN);
/* Enable UARTDM Tx BAM Interface */
data |= UARTDM_TX_BAM_ENABLE_BMSK;
msm_hs_write(uport, UART_DM_DMEN, data);
msm_hs_write(uport, UART_DM_CR, RESET_TX);
msm_hs_write(uport, UART_DM_CR, START_TX_BAM_IFC);
msm_hs_write(uport, UART_DM_CR, UARTDM_CR_TX_EN_BMSK);
MSM_HS_DBG("%s(): TX Connect\n", __func__);
return 0;
reg_event_err:
sps_disconnect(sps_pipe_handle);
return ret;
}
/* Connect a UART peripheral's SPS endpoint(producer endpoint)
*
* Also registers a SPS callback function for the producer
* process with the SPS driver
*
* @uport - Pointer to uart uport structure
*
* @return - 0 if successful else negative value.
*
*/
static int msm_hs_spsconnect_rx(struct uart_port *uport)
{
int ret;
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
struct msm_hs_rx *rx = &msm_uport->rx;
struct sps_pipe *sps_pipe_handle = rx->prod.pipe_handle;
struct sps_connect *sps_config = &rx->prod.config;
struct sps_register_event *sps_event = &rx->prod.event;
unsigned long flags;
/* Establish connection between peripheral and memory endpoint */
ret = sps_connect(sps_pipe_handle, sps_config);
if (ret) {
MSM_HS_ERR("msm_serial_hs: sps_connect() failed for rx\n"
"pipe_handle=0x%pK ret=%d", sps_pipe_handle, ret);
return ret;
}
/* Register callback event for DESC_DONE event. */
ret = sps_register_event(sps_pipe_handle, sps_event);
if (ret) {
MSM_HS_ERR("msm_serial_hs: sps_connect() failed for rx\n"
"pipe_handle=0x%pK ret=%d", sps_pipe_handle, ret);
goto reg_event_err;
}
spin_lock_irqsave(&uport->lock, flags);
if (msm_uport->rx.pending_flag)
MSM_HS_WARN("%s(): Buffers may be pending 0x%lx\n",
__func__, msm_uport->rx.pending_flag);
msm_uport->rx.queued_flag = 0;
msm_uport->rx.pending_flag = 0;
msm_uport->rx.rx_inx = 0;
msm_uport->rx.flush = FLUSH_STOP;
spin_unlock_irqrestore(&uport->lock, flags);
MSM_HS_DBG("%s(): RX Connect\n", __func__);
return 0;
reg_event_err:
sps_disconnect(sps_pipe_handle);
return ret;
}
/*
* programs the UARTDM_CSR register with correct bit rates
*
* Interrupts should be disabled before we are called, as
* we modify Set Baud rate
* Set receive stale interrupt level, dependent on Bit Rate
* Goal is to have around 8 ms before indicate stale.
* roundup (((Bit Rate * .008) / 10) + 1
*/
static void msm_hs_set_bps_locked(struct uart_port *uport,
unsigned int bps)
{
unsigned long rxstale;
unsigned long data;
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
switch (bps) {
case 300:
msm_hs_write(uport, UART_DM_CSR, 0x00);
rxstale = 1;
break;
case 600:
msm_hs_write(uport, UART_DM_CSR, 0x11);
rxstale = 1;
break;
case 1200:
msm_hs_write(uport, UART_DM_CSR, 0x22);
rxstale = 1;
break;
case 2400:
msm_hs_write(uport, UART_DM_CSR, 0x33);
rxstale = 1;
break;
case 4800:
msm_hs_write(uport, UART_DM_CSR, 0x44);
rxstale = 1;
break;
case 9600:
msm_hs_write(uport, UART_DM_CSR, 0x55);
rxstale = 2;
break;
case 14400:
msm_hs_write(uport, UART_DM_CSR, 0x66);
rxstale = 3;
break;
case 19200:
msm_hs_write(uport, UART_DM_CSR, 0x77);
rxstale = 4;
break;
case 28800:
msm_hs_write(uport, UART_DM_CSR, 0x88);
rxstale = 6;
break;
case 38400:
msm_hs_write(uport, UART_DM_CSR, 0x99);
rxstale = 8;
break;
case 57600:
msm_hs_write(uport, UART_DM_CSR, 0xaa);
rxstale = 16;
break;
case 76800:
msm_hs_write(uport, UART_DM_CSR, 0xbb);
rxstale = 16;
break;
case 115200:
msm_hs_write(uport, UART_DM_CSR, 0xcc);
rxstale = 31;
break;
case 230400:
msm_hs_write(uport, UART_DM_CSR, 0xee);
rxstale = 31;
break;
case 460800:
msm_hs_write(uport, UART_DM_CSR, 0xff);
rxstale = 31;
break;
case 4000000:
case 3686400:
case 3200000:
case 3500000:
case 3000000:
case 2500000:
case 2000000:
case 1500000:
case 1152000:
case 1000000:
case 921600:
msm_hs_write(uport, UART_DM_CSR, 0xff);
rxstale = 31;
break;
default:
msm_hs_write(uport, UART_DM_CSR, 0xff);
/* default to 9600 */
bps = 9600;
rxstale = 2;
break;
}
/*
* uart baud rate depends on CSR and MND Values
* we are updating CSR before and then calling
* clk_set_rate which updates MND Values. Hence
* dsb requires here.
*/
mb();
if (bps > 460800) {
uport->uartclk = bps * 16;
/* BLSP based UART supports maximum clock frequency
* of 63.16 Mhz. With this (63.16 Mhz) clock frequency
* UART can support baud rate of 3.94 Mbps which is
* equivalent to 4 Mbps.
* UART hardware is robust enough to handle this
* deviation to achieve baud rate ~4 Mbps.
*/
if (bps == 4000000)
uport->uartclk = BLSP_UART_CLK_FMAX;
} else {
uport->uartclk = 7372800;
}
if (clk_set_rate(msm_uport->clk, uport->uartclk)) {
MSM_HS_WARN("Error setting clock rate on UART\n");
WARN_ON(1);
}
data = rxstale & UARTDM_IPR_STALE_LSB_BMSK;
data |= UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK & (rxstale << 2);
msm_hs_write(uport, UART_DM_IPR, data);
/*
* It is suggested to do reset of transmitter and receiver after
* changing any protocol configuration. Here Baud rate and stale
* timeout are getting updated. Hence reset transmitter and receiver.
*/
msm_hs_write(uport, UART_DM_CR, RESET_TX);
msm_hs_write(uport, UART_DM_CR, RESET_RX);
}
static void msm_hs_set_std_bps_locked(struct uart_port *uport,
unsigned int bps)
{
unsigned long rxstale;
unsigned long data;
switch (bps) {
case 9600:
msm_hs_write(uport, UART_DM_CSR, 0x99);
rxstale = 2;
break;
case 14400:
msm_hs_write(uport, UART_DM_CSR, 0xaa);
rxstale = 3;
break;
case 19200:
msm_hs_write(uport, UART_DM_CSR, 0xbb);