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ixgbe_x550.c
4698 lines (4013 loc) · 130 KB
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ixgbe_x550.c
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/******************************************************************************
Copyright (c) 2001-2020, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the Intel Corporation nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
/*$FreeBSD$*/
#include "ixgbe_x550.h"
#include "ixgbe_x540.h"
#include "ixgbe_type.h"
#include "ixgbe_api.h"
#include "ixgbe_common.h"
#include "ixgbe_phy.h"
static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
static s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
/**
* ixgbe_init_ops_X550 - Inits func ptrs and MAC type
* @hw: pointer to hardware structure
*
* Initialize the function pointers and assign the MAC type for X550.
* Does not touch the hardware.
**/
s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
{
struct ixgbe_mac_info *mac = &hw->mac;
struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
s32 ret_val;
DEBUGFUNC("ixgbe_init_ops_X550");
ret_val = ixgbe_init_ops_X540(hw);
mac->ops.dmac_config = ixgbe_dmac_config_X550;
mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
mac->ops.setup_eee = NULL;
mac->ops.set_source_address_pruning =
ixgbe_set_source_address_pruning_X550;
mac->ops.set_ethertype_anti_spoofing =
ixgbe_set_ethertype_anti_spoofing_X550;
mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
eeprom->ops.read = ixgbe_read_ee_hostif_X550;
eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
eeprom->ops.write = ixgbe_write_ee_hostif_X550;
eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
mac->ops.mdd_event = ixgbe_mdd_event_X550;
mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
mac->ops.fw_recovery_mode = ixgbe_fw_recovery_mode_X550;
mac->ops.disable_rx = ixgbe_disable_rx_x550;
/* Manageability interface */
mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550;
switch (hw->device_id) {
case IXGBE_DEV_ID_X550EM_X_1G_T:
hw->mac.ops.led_on = NULL;
hw->mac.ops.led_off = NULL;
break;
case IXGBE_DEV_ID_X550EM_X_10G_T:
case IXGBE_DEV_ID_X550EM_A_10G_T:
hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
break;
default:
break;
}
return ret_val;
}
/**
* ixgbe_read_cs4227 - Read CS4227 register
* @hw: pointer to hardware structure
* @reg: register number to write
* @value: pointer to receive value read
*
* Returns status code
**/
static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
{
return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
}
/**
* ixgbe_write_cs4227 - Write CS4227 register
* @hw: pointer to hardware structure
* @reg: register number to write
* @value: value to write to register
*
* Returns status code
**/
static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
{
return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
}
/**
* ixgbe_read_pe - Read register from port expander
* @hw: pointer to hardware structure
* @reg: register number to read
* @value: pointer to receive read value
*
* Returns status code
**/
static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
{
s32 status;
status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
if (status != IXGBE_SUCCESS)
ERROR_REPORT2(IXGBE_ERROR_CAUTION,
"port expander access failed with %d\n", status);
return status;
}
/**
* ixgbe_write_pe - Write register to port expander
* @hw: pointer to hardware structure
* @reg: register number to write
* @value: value to write
*
* Returns status code
**/
static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
{
s32 status;
status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
if (status != IXGBE_SUCCESS)
ERROR_REPORT2(IXGBE_ERROR_CAUTION,
"port expander access failed with %d\n", status);
return status;
}
/**
* ixgbe_reset_cs4227 - Reset CS4227 using port expander
* @hw: pointer to hardware structure
*
* This function assumes that the caller has acquired the proper semaphore.
* Returns error code
**/
static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
{
s32 status;
u32 retry;
u16 value;
u8 reg;
/* Trigger hard reset. */
status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
if (status != IXGBE_SUCCESS)
return status;
reg |= IXGBE_PE_BIT1;
status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
if (status != IXGBE_SUCCESS)
return status;
status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
if (status != IXGBE_SUCCESS)
return status;
reg &= ~IXGBE_PE_BIT1;
status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
if (status != IXGBE_SUCCESS)
return status;
status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
if (status != IXGBE_SUCCESS)
return status;
reg &= ~IXGBE_PE_BIT1;
status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
if (status != IXGBE_SUCCESS)
return status;
usec_delay(IXGBE_CS4227_RESET_HOLD);
status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
if (status != IXGBE_SUCCESS)
return status;
reg |= IXGBE_PE_BIT1;
status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
if (status != IXGBE_SUCCESS)
return status;
/* Wait for the reset to complete. */
msec_delay(IXGBE_CS4227_RESET_DELAY);
for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
&value);
if (status == IXGBE_SUCCESS &&
value == IXGBE_CS4227_EEPROM_LOAD_OK)
break;
msec_delay(IXGBE_CS4227_CHECK_DELAY);
}
if (retry == IXGBE_CS4227_RETRIES) {
ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
"CS4227 reset did not complete.");
return IXGBE_ERR_PHY;
}
status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
if (status != IXGBE_SUCCESS ||
!(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
"CS4227 EEPROM did not load successfully.");
return IXGBE_ERR_PHY;
}
return IXGBE_SUCCESS;
}
/**
* ixgbe_check_cs4227 - Check CS4227 and reset as needed
* @hw: pointer to hardware structure
**/
static void ixgbe_check_cs4227(struct ixgbe_hw *hw)
{
s32 status = IXGBE_SUCCESS;
u32 swfw_mask = hw->phy.phy_semaphore_mask;
u16 value = 0;
u8 retry;
for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
if (status != IXGBE_SUCCESS) {
ERROR_REPORT2(IXGBE_ERROR_CAUTION,
"semaphore failed with %d", status);
msec_delay(IXGBE_CS4227_CHECK_DELAY);
continue;
}
/* Get status of reset flow. */
status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
if (status == IXGBE_SUCCESS &&
value == IXGBE_CS4227_RESET_COMPLETE)
goto out;
if (status != IXGBE_SUCCESS ||
value != IXGBE_CS4227_RESET_PENDING)
break;
/* Reset is pending. Wait and check again. */
hw->mac.ops.release_swfw_sync(hw, swfw_mask);
msec_delay(IXGBE_CS4227_CHECK_DELAY);
}
/* If still pending, assume other instance failed. */
if (retry == IXGBE_CS4227_RETRIES) {
status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
if (status != IXGBE_SUCCESS) {
ERROR_REPORT2(IXGBE_ERROR_CAUTION,
"semaphore failed with %d", status);
return;
}
}
/* Reset the CS4227. */
status = ixgbe_reset_cs4227(hw);
if (status != IXGBE_SUCCESS) {
ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
"CS4227 reset failed: %d", status);
goto out;
}
/* Reset takes so long, temporarily release semaphore in case the
* other driver instance is waiting for the reset indication.
*/
ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
IXGBE_CS4227_RESET_PENDING);
hw->mac.ops.release_swfw_sync(hw, swfw_mask);
msec_delay(10);
status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
if (status != IXGBE_SUCCESS) {
ERROR_REPORT2(IXGBE_ERROR_CAUTION,
"semaphore failed with %d", status);
return;
}
/* Record completion for next time. */
status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
IXGBE_CS4227_RESET_COMPLETE);
out:
hw->mac.ops.release_swfw_sync(hw, swfw_mask);
msec_delay(hw->eeprom.semaphore_delay);
}
/**
* ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
* @hw: pointer to hardware structure
**/
static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
{
u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
if (hw->bus.lan_id) {
esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
esdp |= IXGBE_ESDP_SDP1_DIR;
}
esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
IXGBE_WRITE_FLUSH(hw);
}
/**
* ixgbe_identify_phy_x550em - Get PHY type based on device id
* @hw: pointer to hardware structure
*
* Returns error code
*/
static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
{
hw->mac.ops.set_lan_id(hw);
ixgbe_read_mng_if_sel_x550em(hw);
switch (hw->device_id) {
case IXGBE_DEV_ID_X550EM_A_SFP:
return ixgbe_identify_sfp_module_X550em(hw);
case IXGBE_DEV_ID_X550EM_X_SFP:
/* set up for CS4227 usage */
ixgbe_setup_mux_ctl(hw);
ixgbe_check_cs4227(hw);
/* Fallthrough */
case IXGBE_DEV_ID_X550EM_A_SFP_N:
return ixgbe_identify_sfp_module_X550em(hw);
break;
case IXGBE_DEV_ID_X550EM_X_KX4:
hw->phy.type = ixgbe_phy_x550em_kx4;
break;
case IXGBE_DEV_ID_X550EM_X_XFI:
hw->phy.type = ixgbe_phy_x550em_xfi;
break;
case IXGBE_DEV_ID_X550EM_X_KR:
case IXGBE_DEV_ID_X550EM_A_KR:
case IXGBE_DEV_ID_X550EM_A_KR_L:
hw->phy.type = ixgbe_phy_x550em_kr;
break;
case IXGBE_DEV_ID_X550EM_A_10G_T:
case IXGBE_DEV_ID_X550EM_X_10G_T:
return ixgbe_identify_phy_generic(hw);
case IXGBE_DEV_ID_X550EM_X_1G_T:
hw->phy.type = ixgbe_phy_ext_1g_t;
break;
case IXGBE_DEV_ID_X550EM_A_1G_T:
case IXGBE_DEV_ID_X550EM_A_1G_T_L:
hw->phy.type = ixgbe_phy_fw;
if (hw->bus.lan_id)
hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
else
hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
break;
default:
break;
}
return IXGBE_SUCCESS;
}
/**
* ixgbe_fw_phy_activity - Perform an activity on a PHY
* @hw: pointer to hardware structure
* @activity: activity to perform
* @data: Pointer to 4 32-bit words of data
*/
s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
u32 (*data)[FW_PHY_ACT_DATA_COUNT])
{
union {
struct ixgbe_hic_phy_activity_req cmd;
struct ixgbe_hic_phy_activity_resp rsp;
} hic;
u16 retries = FW_PHY_ACT_RETRIES;
s32 rc;
u16 i;
do {
memset(&hic, 0, sizeof(hic));
hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
hic.cmd.port_number = hw->bus.lan_id;
hic.cmd.activity_id = IXGBE_CPU_TO_LE16(activity);
for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
hic.cmd.data[i] = IXGBE_CPU_TO_BE32((*data)[i]);
rc = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
sizeof(hic.cmd),
IXGBE_HI_COMMAND_TIMEOUT,
true);
if (rc != IXGBE_SUCCESS)
return rc;
if (hic.rsp.hdr.cmd_or_resp.ret_status ==
FW_CEM_RESP_STATUS_SUCCESS) {
for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
(*data)[i] = IXGBE_BE32_TO_CPU(hic.rsp.data[i]);
return IXGBE_SUCCESS;
}
usec_delay(20);
--retries;
} while (retries > 0);
return IXGBE_ERR_HOST_INTERFACE_COMMAND;
}
static const struct {
u16 fw_speed;
ixgbe_link_speed phy_speed;
} ixgbe_fw_map[] = {
{ FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
{ FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
{ FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
{ FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
{ FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
{ FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
};
/**
* ixgbe_get_phy_id_fw - Get the phy ID via firmware command
* @hw: pointer to hardware structure
*
* Returns error code
*/
static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
{
u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
u16 phy_speeds;
u16 phy_id_lo;
s32 rc;
u16 i;
rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
if (rc)
return rc;
hw->phy.speeds_supported = 0;
phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
if (phy_speeds & ixgbe_fw_map[i].fw_speed)
hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
}
if (!hw->phy.autoneg_advertised)
hw->phy.autoneg_advertised = hw->phy.speeds_supported;
hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
return IXGBE_ERR_PHY_ADDR_INVALID;
return IXGBE_SUCCESS;
}
/**
* ixgbe_identify_phy_fw - Get PHY type based on firmware command
* @hw: pointer to hardware structure
*
* Returns error code
*/
static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
{
if (hw->bus.lan_id)
hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
else
hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
hw->phy.type = ixgbe_phy_fw;
hw->phy.ops.read_reg = NULL;
hw->phy.ops.write_reg = NULL;
return ixgbe_get_phy_id_fw(hw);
}
/**
* ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
* @hw: pointer to hardware structure
*
* Returns error code
*/
s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
{
u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
}
static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
u32 device_type, u16 *phy_data)
{
UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
return IXGBE_NOT_IMPLEMENTED;
}
static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
u32 device_type, u16 phy_data)
{
UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
return IXGBE_NOT_IMPLEMENTED;
}
/**
* ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
* @hw: pointer to the hardware structure
* @addr: I2C bus address to read from
* @reg: I2C device register to read from
* @val: pointer to location to receive read value
*
* Returns an error code on error.
**/
static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
u16 reg, u16 *val)
{
return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
}
/**
* ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
* @hw: pointer to the hardware structure
* @addr: I2C bus address to read from
* @reg: I2C device register to read from
* @val: pointer to location to receive read value
*
* Returns an error code on error.
**/
static s32
ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
u16 reg, u16 *val)
{
return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
}
/**
* ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
* @hw: pointer to the hardware structure
* @addr: I2C bus address to write to
* @reg: I2C device register to write to
* @val: value to write
*
* Returns an error code on error.
**/
static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
u8 addr, u16 reg, u16 val)
{
return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
}
/**
* ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
* @hw: pointer to the hardware structure
* @addr: I2C bus address to write to
* @reg: I2C device register to write to
* @val: value to write
*
* Returns an error code on error.
**/
static s32
ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
u8 addr, u16 reg, u16 val)
{
return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
}
/**
* ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
* @hw: pointer to hardware structure
*
* Initialize the function pointers and for MAC type X550EM.
* Does not touch the hardware.
**/
s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
{
struct ixgbe_mac_info *mac = &hw->mac;
struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
struct ixgbe_phy_info *phy = &hw->phy;
s32 ret_val;
DEBUGFUNC("ixgbe_init_ops_X550EM");
/* Similar to X550 so start there. */
ret_val = ixgbe_init_ops_X550(hw);
/* Since this function eventually calls
* ixgbe_init_ops_540 by design, we are setting
* the pointers to NULL explicitly here to overwrite
* the values being set in the x540 function.
*/
/* Thermal sensor not supported in x550EM */
mac->ops.get_thermal_sensor_data = NULL;
mac->ops.init_thermal_sensor_thresh = NULL;
mac->thermal_sensor_enabled = false;
/* Bypass not supported in x550EM */
mac->ops.bypass_rw = NULL;
mac->ops.bypass_valid_rd = NULL;
mac->ops.bypass_set = NULL;
mac->ops.bypass_rd_eep = NULL;
/* FCOE not supported in x550EM */
mac->ops.get_san_mac_addr = NULL;
mac->ops.set_san_mac_addr = NULL;
mac->ops.get_wwn_prefix = NULL;
mac->ops.get_fcoe_boot_status = NULL;
/* IPsec not supported in x550EM */
mac->ops.disable_sec_rx_path = NULL;
mac->ops.enable_sec_rx_path = NULL;
/* AUTOC register is not present in x550EM. */
mac->ops.prot_autoc_read = NULL;
mac->ops.prot_autoc_write = NULL;
/* X550EM bus type is internal*/
hw->bus.type = ixgbe_bus_type_internal;
mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
mac->ops.get_media_type = ixgbe_get_media_type_X550em;
mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
mac->ops.reset_hw = ixgbe_reset_hw_X550em;
mac->ops.get_supported_physical_layer =
ixgbe_get_supported_physical_layer_X550em;
if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
mac->ops.setup_fc = ixgbe_setup_fc_generic;
else
mac->ops.setup_fc = ixgbe_setup_fc_X550em;
/* PHY */
phy->ops.init = ixgbe_init_phy_ops_X550em;
switch (hw->device_id) {
case IXGBE_DEV_ID_X550EM_A_1G_T:
case IXGBE_DEV_ID_X550EM_A_1G_T_L:
mac->ops.setup_fc = NULL;
phy->ops.identify = ixgbe_identify_phy_fw;
phy->ops.set_phy_power = NULL;
phy->ops.get_firmware_version = NULL;
break;
case IXGBE_DEV_ID_X550EM_X_1G_T:
mac->ops.setup_fc = NULL;
phy->ops.identify = ixgbe_identify_phy_x550em;
phy->ops.set_phy_power = NULL;
break;
default:
phy->ops.identify = ixgbe_identify_phy_x550em;
}
if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
phy->ops.set_phy_power = NULL;
/* EEPROM */
eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
eeprom->ops.read = ixgbe_read_ee_hostif_X550;
eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
eeprom->ops.write = ixgbe_write_ee_hostif_X550;
eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
return ret_val;
}
/**
* ixgbe_setup_fw_link - Setup firmware-controlled PHYs
* @hw: pointer to hardware structure
*/
static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
{
u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
s32 rc;
u16 i;
if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
return 0;
if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
"ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
return IXGBE_ERR_INVALID_LINK_SETTINGS;
}
switch (hw->fc.requested_mode) {
case ixgbe_fc_full:
setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
break;
case ixgbe_fc_rx_pause:
setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
break;
case ixgbe_fc_tx_pause:
setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
break;
default:
break;
}
for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
setup[0] |= (u32)(ixgbe_fw_map[i].fw_speed);
}
setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
if (hw->phy.eee_speeds_advertised)
setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
if (rc)
return rc;
if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
return IXGBE_ERR_OVERTEMP;
return IXGBE_SUCCESS;
}
/**
* ixgbe_fc_autoneg_fw _ Set up flow control for FW-controlled PHYs
* @hw: pointer to hardware structure
*
* Called at init time to set up flow control.
*/
static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
{
if (hw->fc.requested_mode == ixgbe_fc_default)
hw->fc.requested_mode = ixgbe_fc_full;
return ixgbe_setup_fw_link(hw);
}
/**
* ixgbe_setup_eee_fw - Enable/disable EEE support
* @hw: pointer to the HW structure
* @enable_eee: boolean flag to enable EEE
*
* Enable/disable EEE based on enable_eee flag.
* This function controls EEE for firmware-based PHY implementations.
*/
static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee)
{
if (!!hw->phy.eee_speeds_advertised == enable_eee)
return IXGBE_SUCCESS;
if (enable_eee)
hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
else
hw->phy.eee_speeds_advertised = 0;
return hw->phy.ops.setup_link(hw);
}
/**
* ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
* @hw: pointer to hardware structure
*
* Initialize the function pointers and for MAC type X550EM_a.
* Does not touch the hardware.
**/
s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
{
struct ixgbe_mac_info *mac = &hw->mac;
s32 ret_val;
DEBUGFUNC("ixgbe_init_ops_X550EM_a");
/* Start with generic X550EM init */
ret_val = ixgbe_init_ops_X550EM(hw);
if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
} else {
mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
}
mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
switch (mac->ops.get_media_type(hw)) {
case ixgbe_media_type_fiber:
mac->ops.setup_fc = NULL;
mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
break;
case ixgbe_media_type_backplane:
mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
break;
default:
break;
}
switch (hw->device_id) {
case IXGBE_DEV_ID_X550EM_A_1G_T:
case IXGBE_DEV_ID_X550EM_A_1G_T_L:
mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
mac->ops.setup_eee = ixgbe_setup_eee_fw;
hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
IXGBE_LINK_SPEED_1GB_FULL;
hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
break;
default:
break;
}
return ret_val;
}
/**
* ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
* @hw: pointer to hardware structure
*
* Initialize the function pointers and for MAC type X550EM_x.
* Does not touch the hardware.
**/
s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
{
struct ixgbe_mac_info *mac = &hw->mac;
struct ixgbe_link_info *link = &hw->link;
s32 ret_val;
DEBUGFUNC("ixgbe_init_ops_X550EM_x");
/* Start with generic X550EM init */
ret_val = ixgbe_init_ops_X550EM(hw);
mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
link->ops.read_link = ixgbe_read_i2c_combined_generic;
link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
link->ops.write_link = ixgbe_write_i2c_combined_generic;
link->ops.write_link_unlocked =
ixgbe_write_i2c_combined_generic_unlocked;
link->addr = IXGBE_CS4227;
if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) {
mac->ops.setup_fc = NULL;
mac->ops.setup_eee = NULL;
mac->ops.init_led_link_act = NULL;
}
return ret_val;
}
/**
* ixgbe_dmac_config_X550
* @hw: pointer to hardware structure
*
* Configure DMA coalescing. If enabling dmac, dmac is activated.
* When disabling dmac, dmac enable dmac bit is cleared.
**/
s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
{
u32 reg, high_pri_tc;
DEBUGFUNC("ixgbe_dmac_config_X550");
/* Disable DMA coalescing before configuring */
reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
reg &= ~IXGBE_DMACR_DMAC_EN;
IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
/* Disable DMA Coalescing if the watchdog timer is 0 */
if (!hw->mac.dmac_config.watchdog_timer)
goto out;
ixgbe_dmac_config_tcs_X550(hw);
/* Configure DMA Coalescing Control Register */
reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
/* Set the watchdog timer in units of 40.96 usec */
reg &= ~IXGBE_DMACR_DMACWT_MASK;
reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
/* If fcoe is enabled, set high priority traffic class */
if (hw->mac.dmac_config.fcoe_en) {
high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
IXGBE_DMACR_HIGH_PRI_TC_MASK);
}
reg |= IXGBE_DMACR_EN_MNG_IND;
/* Enable DMA coalescing after configuration */
reg |= IXGBE_DMACR_DMAC_EN;
IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
out:
return IXGBE_SUCCESS;
}
/**
* ixgbe_dmac_config_tcs_X550
* @hw: pointer to hardware structure
*
* Configure DMA coalescing threshold per TC. The dmac enable bit must
* be cleared before configuring.
**/
s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
{
u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
/* Configure DMA coalescing enabled */
switch (hw->mac.dmac_config.link_speed) {
case IXGBE_LINK_SPEED_10_FULL:
case IXGBE_LINK_SPEED_100_FULL:
pb_headroom = IXGBE_DMACRXT_100M;
break;
case IXGBE_LINK_SPEED_1GB_FULL:
pb_headroom = IXGBE_DMACRXT_1G;
break;
default:
pb_headroom = IXGBE_DMACRXT_10G;
break;
}
maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
IXGBE_MHADD_MFS_SHIFT) / 1024);
/* Set the per Rx packet buffer receive threshold */
for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
if (tc < hw->mac.dmac_config.num_tcs) {
/* Get Rx PB size */
rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
IXGBE_RXPBSIZE_SHIFT;
/* Calculate receive buffer threshold in kilobytes */
if (rx_pb_size > pb_headroom)
rx_pb_size = rx_pb_size - pb_headroom;
else
rx_pb_size = 0;
/* Minimum of MFS shall be set for DMCTH */
reg |= (rx_pb_size > maxframe_size_kb) ?
rx_pb_size : maxframe_size_kb;
}
IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
}
return IXGBE_SUCCESS;
}
/**
* ixgbe_dmac_update_tcs_X550
* @hw: pointer to hardware structure
*
* Disables dmac, updates per TC settings, and then enables dmac.
**/
s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
{
u32 reg;
DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
/* Disable DMA coalescing before configuring */
reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
reg &= ~IXGBE_DMACR_DMAC_EN;