-
Notifications
You must be signed in to change notification settings - Fork 2.8k
/
at91_mci.c
1404 lines (1249 loc) · 41.1 KB
/
at91_mci.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*-
* Copyright (c) 2006 Bernd Walter. All rights reserved.
* Copyright (c) 2006 M. Warner Losh. All rights reserved.
* Copyright (c) 2010 Greg Ansley. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include "opt_platform.h"
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/endian.h>
#include <sys/kernel.h>
#include <sys/lock.h>
#include <sys/malloc.h>
#include <sys/module.h>
#include <sys/mutex.h>
#include <sys/resource.h>
#include <sys/rman.h>
#include <sys/sysctl.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <machine/intr.h>
#include <arm/at91/at91var.h>
#include <arm/at91/at91_mcireg.h>
#include <arm/at91/at91_pdcreg.h>
#include <dev/mmc/bridge.h>
#include <dev/mmc/mmcbrvar.h>
#ifdef FDT
#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>
#endif
#include "mmcbr_if.h"
#include "opt_at91.h"
/*
* About running the MCI bus above 25MHz
*
* Historically, the MCI bus has been run at 30MHz on systems with a 60MHz
* master clock, in part due to a bug in dev/mmc.c making always request
* 30MHz, and in part over clocking the bus because 15MHz was too slow.
* Fixing that bug causes the mmc driver to request a 25MHz clock (as it
* should) and the logic in at91_mci_update_ios() picks the highest speed that
* doesn't exceed that limit. With a 60MHz MCK that would be 15MHz, and
* that's a real performance buzzkill when you've been getting away with 30MHz
* all along.
*
* By defining AT91_MCI_ALLOW_OVERCLOCK (or setting the allow_overclock=1
* device hint or sysctl) you can enable logic in at91_mci_update_ios() to
* overlcock the SD bus a little by running it at MCK / 2 when the requested
* speed is 25MHz and the next highest speed is 15MHz or less. This appears
* to work on virtually all SD cards, since it is what this driver has been
* doing prior to the introduction of this option, where the overclocking vs
* underclocking decision was automatically "overclock". Modern SD cards can
* run at 45mhz/1-bit in standard mode (high speed mode enable commands not
* sent) without problems.
*
* Speaking of high-speed mode, the rm9200 manual says the MCI device supports
* the SD v1.0 specification and can run up to 50MHz. This is interesting in
* that the SD v1.0 spec caps the speed at 25MHz; high speed mode was added in
* the v1.10 spec. Furthermore, high speed mode doesn't just crank up the
* clock, it alters the signal timing. The rm9200 MCI device doesn't support
* these altered timings. So while speeds over 25MHz may work, they only work
* in what the SD spec calls "default" speed mode, and it amounts to violating
* the spec by overclocking the bus.
*
* If you also enable 4-wire mode it's possible transfers faster than 25MHz
* will fail. On the AT91RM9200, due to bugs in the bus contention logic, if
* you have the USB host device and OHCI driver enabled will fail. Even
* underclocking to 15MHz, intermittant overrun and underrun errors occur.
* Note that you don't even need to have usb devices attached to the system,
* the errors begin to occur as soon as the OHCI driver sets the register bit
* to enable periodic transfers. It appears (based on brief investigation)
* that the usb host controller uses so much ASB bandwidth that sometimes the
* DMA for MCI transfers doesn't get a bus grant in time and data gets
* dropped. Adding even a modicum of network activity changes the symptom
* from intermittant to very frequent. Members of the AT91SAM9 family have
* corrected this problem, or are at least better about their use of the bus.
*/
#ifndef AT91_MCI_ALLOW_OVERCLOCK
#define AT91_MCI_ALLOW_OVERCLOCK 1
#endif
/*
* Allocate 2 bounce buffers we'll use to endian-swap the data due to the rm9200
* erratum. We use a pair of buffers because when reading that lets us begin
* endian-swapping the data in the first buffer while the DMA is reading into
* the second buffer. (We can't use the same trick for writing because we might
* not get all the data in the 2nd buffer swapped before the hardware needs it;
* dealing with that would add complexity to the driver.)
*
* The buffers are sized at 16K each due to the way the busdma cache sync
* operations work on arm. A dcache_inv_range() operation on a range larger
* than 16K gets turned into a dcache_wbinv_all(). That needlessly flushes the
* entire data cache, impacting overall system performance.
*/
#define BBCOUNT 2
#define BBSIZE (16*1024)
#define MAX_BLOCKS ((BBSIZE*BBCOUNT)/512)
static int mci_debug;
struct at91_mci_softc {
void *intrhand; /* Interrupt handle */
device_t dev;
int sc_cap;
#define CAP_HAS_4WIRE 1 /* Has 4 wire bus */
#define CAP_NEEDS_BYTESWAP 2 /* broken hardware needing bounce */
#define CAP_MCI1_REV2XX 4 /* MCI 1 rev 2.x */
int flags;
#define PENDING_CMD 0x01
#define PENDING_STOP 0x02
#define CMD_MULTIREAD 0x10
#define CMD_MULTIWRITE 0x20
int has_4wire;
int allow_overclock;
struct resource *irq_res; /* IRQ resource */
struct resource *mem_res; /* Memory resource */
struct mtx sc_mtx;
bus_dma_tag_t dmatag;
struct mmc_host host;
int bus_busy;
struct mmc_request *req;
struct mmc_command *curcmd;
bus_dmamap_t bbuf_map[BBCOUNT];
char * bbuf_vaddr[BBCOUNT]; /* bounce bufs in KVA space */
uint32_t bbuf_len[BBCOUNT]; /* len currently queued for bounce buf */
uint32_t bbuf_curidx; /* which bbuf is the active DMA buffer */
uint32_t xfer_offset; /* offset so far into caller's buf */
};
/* bus entry points */
static int at91_mci_probe(device_t dev);
static int at91_mci_attach(device_t dev);
static int at91_mci_detach(device_t dev);
static void at91_mci_intr(void *);
/* helper routines */
static int at91_mci_activate(device_t dev);
static void at91_mci_deactivate(device_t dev);
static int at91_mci_is_mci1rev2xx(void);
#define AT91_MCI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
#define AT91_MCI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
#define AT91_MCI_LOCK_INIT(_sc) \
mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
"mci", MTX_DEF)
#define AT91_MCI_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
#define AT91_MCI_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
#define AT91_MCI_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
static inline uint32_t
RD4(struct at91_mci_softc *sc, bus_size_t off)
{
return (bus_read_4(sc->mem_res, off));
}
static inline void
WR4(struct at91_mci_softc *sc, bus_size_t off, uint32_t val)
{
bus_write_4(sc->mem_res, off, val);
}
static void
at91_bswap_buf(struct at91_mci_softc *sc, void * dptr, void * sptr, uint32_t memsize)
{
uint32_t * dst = (uint32_t *)dptr;
uint32_t * src = (uint32_t *)sptr;
uint32_t i;
/*
* If the hardware doesn't need byte-swapping, let bcopy() do the
* work. Use bounce buffer even if we don't need byteswap, since
* buffer may straddle a page boundary, and we don't handle
* multi-segment transfers in hardware. Seen from 'bsdlabel -w' which
* uses raw geom access to the volume. Greg Ansley (gja (at)
* ansley.com)
*/
if (!(sc->sc_cap & CAP_NEEDS_BYTESWAP)) {
memcpy(dptr, sptr, memsize);
return;
}
/*
* Nice performance boost for slightly unrolling this loop.
* (But very little extra boost for further unrolling it.)
*/
for (i = 0; i < memsize; i += 16) {
*dst++ = bswap32(*src++);
*dst++ = bswap32(*src++);
*dst++ = bswap32(*src++);
*dst++ = bswap32(*src++);
}
/* Mop up the last 1-3 words, if any. */
for (i = 0; i < (memsize & 0x0F); i += 4) {
*dst++ = bswap32(*src++);
}
}
static void
at91_mci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
{
if (error != 0)
return;
*(bus_addr_t *)arg = segs[0].ds_addr;
}
static void
at91_mci_pdc_disable(struct at91_mci_softc *sc)
{
WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS);
WR4(sc, PDC_RPR, 0);
WR4(sc, PDC_RCR, 0);
WR4(sc, PDC_RNPR, 0);
WR4(sc, PDC_RNCR, 0);
WR4(sc, PDC_TPR, 0);
WR4(sc, PDC_TCR, 0);
WR4(sc, PDC_TNPR, 0);
WR4(sc, PDC_TNCR, 0);
}
/*
* Reset the controller, then restore most of the current state.
*
* This is called after detecting an error. It's also called after stopping a
* multi-block write, to un-wedge the device so that it will handle the NOTBUSY
* signal correctly. See comments in at91_mci_stop_done() for more details.
*/
static void at91_mci_reset(struct at91_mci_softc *sc)
{
uint32_t mr;
uint32_t sdcr;
uint32_t dtor;
uint32_t imr;
at91_mci_pdc_disable(sc);
/* save current state */
imr = RD4(sc, MCI_IMR);
mr = RD4(sc, MCI_MR) & 0x7fff;
sdcr = RD4(sc, MCI_SDCR);
dtor = RD4(sc, MCI_DTOR);
/* reset the controller */
WR4(sc, MCI_IDR, 0xffffffff);
WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST);
/* restore state */
WR4(sc, MCI_CR, MCI_CR_MCIEN|MCI_CR_PWSEN);
WR4(sc, MCI_MR, mr);
WR4(sc, MCI_SDCR, sdcr);
WR4(sc, MCI_DTOR, dtor);
WR4(sc, MCI_IER, imr);
/*
* Make sure sdio interrupts will fire. Not sure why reading
* SR ensures that, but this is in the linux driver.
*/
RD4(sc, MCI_SR);
}
static void
at91_mci_init(device_t dev)
{
struct at91_mci_softc *sc = device_get_softc(dev);
uint32_t val;
WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST); /* device into reset */
WR4(sc, MCI_IDR, 0xffffffff); /* Turn off interrupts */
WR4(sc, MCI_DTOR, MCI_DTOR_DTOMUL_1M | 1);
val = MCI_MR_PDCMODE;
val |= 0x34a; /* PWSDIV = 3; CLKDIV = 74 */
// if (sc->sc_cap & CAP_MCI1_REV2XX)
// val |= MCI_MR_RDPROOF | MCI_MR_WRPROOF;
WR4(sc, MCI_MR, val);
#ifndef AT91_MCI_SLOT_B
WR4(sc, MCI_SDCR, 0); /* SLOT A, 1 bit bus */
#else
/*
* XXX Really should add second "unit" but nobody using using
* a two slot card that we know of. XXX
*/
WR4(sc, MCI_SDCR, 1); /* SLOT B, 1 bit bus */
#endif
/*
* Enable controller, including power-save. The slower clock
* of the power-save mode is only in effect when there is no
* transfer in progress, so it can be left in this mode all
* the time.
*/
WR4(sc, MCI_CR, MCI_CR_MCIEN|MCI_CR_PWSEN);
}
static void
at91_mci_fini(device_t dev)
{
struct at91_mci_softc *sc = device_get_softc(dev);
WR4(sc, MCI_IDR, 0xffffffff); /* Turn off interrupts */
at91_mci_pdc_disable(sc);
WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST); /* device into reset */
}
static int
at91_mci_probe(device_t dev)
{
#ifdef FDT
if (!ofw_bus_is_compatible(dev, "atmel,hsmci"))
return (ENXIO);
#endif
device_set_desc(dev, "MCI mmc/sd host bridge");
return (0);
}
static int
at91_mci_attach(device_t dev)
{
struct at91_mci_softc *sc = device_get_softc(dev);
struct sysctl_ctx_list *sctx;
struct sysctl_oid *soid;
device_t child;
int err, i;
sctx = device_get_sysctl_ctx(dev);
soid = device_get_sysctl_tree(dev);
sc->dev = dev;
sc->sc_cap = 0;
if (at91_is_rm92())
sc->sc_cap |= CAP_NEEDS_BYTESWAP;
/*
* MCI1 Rev 2 controllers need some workarounds, flag if so.
*/
if (at91_mci_is_mci1rev2xx())
sc->sc_cap |= CAP_MCI1_REV2XX;
err = at91_mci_activate(dev);
if (err)
goto out;
AT91_MCI_LOCK_INIT(sc);
at91_mci_fini(dev);
at91_mci_init(dev);
/*
* Allocate DMA tags and maps and bounce buffers.
*
* The parms in the tag_create call cause the dmamem_alloc call to
* create each bounce buffer as a single contiguous buffer of BBSIZE
* bytes aligned to a 4096 byte boundary.
*
* Do not use DMA_COHERENT for these buffers because that maps the
* memory as non-cachable, which prevents cache line burst fills/writes,
* which is something we need since we're trying to overlap the
* byte-swapping with the DMA operations.
*/
err = bus_dma_tag_create(bus_get_dma_tag(dev), 4096, 0,
BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
BBSIZE, 1, BBSIZE, 0, NULL, NULL, &sc->dmatag);
if (err != 0)
goto out;
for (i = 0; i < BBCOUNT; ++i) {
err = bus_dmamem_alloc(sc->dmatag, (void **)&sc->bbuf_vaddr[i],
BUS_DMA_NOWAIT, &sc->bbuf_map[i]);
if (err != 0)
goto out;
}
/*
* Activate the interrupt
*/
err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
NULL, at91_mci_intr, sc, &sc->intrhand);
if (err) {
AT91_MCI_LOCK_DESTROY(sc);
goto out;
}
/*
* Allow 4-wire to be initially set via #define.
* Allow a device hint to override that.
* Allow a sysctl to override that.
*/
#if defined(AT91_MCI_HAS_4WIRE) && AT91_MCI_HAS_4WIRE != 0
sc->has_4wire = 1;
#endif
resource_int_value(device_get_name(dev), device_get_unit(dev),
"4wire", &sc->has_4wire);
SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "4wire",
CTLFLAG_RW, &sc->has_4wire, 0, "has 4 wire SD Card bus");
if (sc->has_4wire)
sc->sc_cap |= CAP_HAS_4WIRE;
sc->allow_overclock = AT91_MCI_ALLOW_OVERCLOCK;
resource_int_value(device_get_name(dev), device_get_unit(dev),
"allow_overclock", &sc->allow_overclock);
SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "allow_overclock",
CTLFLAG_RW, &sc->allow_overclock, 0,
"Allow up to 30MHz clock for 25MHz request when next highest speed 15MHz or less.");
SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "debug",
CTLFLAG_RWTUN, &mci_debug, 0, "enable debug output");
/*
* Our real min freq is master_clock/512, but upper driver layers are
* going to set the min speed during card discovery, and the right speed
* for that is 400kHz, so advertise a safe value just under that.
*
* For max speed, while the rm9200 manual says the max is 50mhz, it also
* says it supports only the SD v1.0 spec, which means the real limit is
* 25mhz. On the other hand, historical use has been to slightly violate
* the standard by running the bus at 30MHz. For more information on
* that, see the comments at the top of this file.
*/
sc->host.f_min = 375000;
sc->host.f_max = at91_master_clock / 2;
if (sc->host.f_max > 25000000)
sc->host.f_max = 25000000;
sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
sc->host.caps = 0;
if (sc->sc_cap & CAP_HAS_4WIRE)
sc->host.caps |= MMC_CAP_4_BIT_DATA;
child = device_add_child(dev, "mmc", 0);
device_set_ivars(dev, &sc->host);
err = bus_generic_attach(dev);
out:
if (err)
at91_mci_deactivate(dev);
return (err);
}
static int
at91_mci_detach(device_t dev)
{
struct at91_mci_softc *sc = device_get_softc(dev);
at91_mci_fini(dev);
at91_mci_deactivate(dev);
bus_dmamem_free(sc->dmatag, sc->bbuf_vaddr[0], sc->bbuf_map[0]);
bus_dmamem_free(sc->dmatag, sc->bbuf_vaddr[1], sc->bbuf_map[1]);
bus_dma_tag_destroy(sc->dmatag);
return (EBUSY); /* XXX */
}
static int
at91_mci_activate(device_t dev)
{
struct at91_mci_softc *sc;
int rid;
sc = device_get_softc(dev);
rid = 0;
sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (sc->mem_res == NULL)
goto errout;
rid = 0;
sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_ACTIVE);
if (sc->irq_res == NULL)
goto errout;
return (0);
errout:
at91_mci_deactivate(dev);
return (ENOMEM);
}
static void
at91_mci_deactivate(device_t dev)
{
struct at91_mci_softc *sc;
sc = device_get_softc(dev);
if (sc->intrhand)
bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
sc->intrhand = NULL;
bus_generic_detach(sc->dev);
if (sc->mem_res)
bus_release_resource(dev, SYS_RES_MEMORY,
rman_get_rid(sc->mem_res), sc->mem_res);
sc->mem_res = NULL;
if (sc->irq_res)
bus_release_resource(dev, SYS_RES_IRQ,
rman_get_rid(sc->irq_res), sc->irq_res);
sc->irq_res = NULL;
return;
}
static int
at91_mci_is_mci1rev2xx(void)
{
switch (soc_info.type) {
case AT91_T_SAM9260:
case AT91_T_SAM9263:
case AT91_T_CAP9:
case AT91_T_SAM9G10:
case AT91_T_SAM9G20:
case AT91_T_SAM9RL:
return(1);
default:
return (0);
}
}
static int
at91_mci_update_ios(device_t brdev, device_t reqdev)
{
struct at91_mci_softc *sc;
struct mmc_ios *ios;
uint32_t clkdiv;
uint32_t freq;
sc = device_get_softc(brdev);
ios = &sc->host.ios;
/*
* Calculate our closest available clock speed that doesn't exceed the
* requested speed.
*
* When overclocking is allowed, the requested clock is 25MHz, the
* computed frequency is 15MHz or smaller and clockdiv is 1, use
* clockdiv of 0 to double that. If less than 12.5MHz, double
* regardless of the overclocking setting.
*
* Whatever we come up with, store it back into ios->clock so that the
* upper layer drivers can report the actual speed of the bus.
*/
if (ios->clock == 0) {
WR4(sc, MCI_CR, MCI_CR_MCIDIS);
clkdiv = 0;
} else {
WR4(sc, MCI_CR, MCI_CR_MCIEN|MCI_CR_PWSEN);
if ((at91_master_clock % (ios->clock * 2)) == 0)
clkdiv = ((at91_master_clock / ios->clock) / 2) - 1;
else
clkdiv = (at91_master_clock / ios->clock) / 2;
freq = at91_master_clock / ((clkdiv+1) * 2);
if (clkdiv == 1 && ios->clock == 25000000 && freq <= 15000000) {
if (sc->allow_overclock || freq <= 12500000) {
clkdiv = 0;
freq = at91_master_clock / ((clkdiv+1) * 2);
}
}
ios->clock = freq;
}
if (ios->bus_width == bus_width_4)
WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) | MCI_SDCR_SDCBUS);
else
WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) & ~MCI_SDCR_SDCBUS);
WR4(sc, MCI_MR, (RD4(sc, MCI_MR) & ~MCI_MR_CLKDIV) | clkdiv);
/* Do we need a settle time here? */
/* XXX We need to turn the device on/off here with a GPIO pin */
return (0);
}
static void
at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd)
{
uint32_t cmdr, mr;
struct mmc_data *data;
sc->curcmd = cmd;
data = cmd->data;
/* XXX Upper layers don't always set this */
cmd->mrq = sc->req;
/* Begin setting up command register. */
cmdr = cmd->opcode;
if (sc->host.ios.bus_mode == opendrain)
cmdr |= MCI_CMDR_OPDCMD;
/* Set up response handling. Allow max timeout for responses. */
if (MMC_RSP(cmd->flags) == MMC_RSP_NONE)
cmdr |= MCI_CMDR_RSPTYP_NO;
else {
cmdr |= MCI_CMDR_MAXLAT;
if (cmd->flags & MMC_RSP_136)
cmdr |= MCI_CMDR_RSPTYP_136;
else
cmdr |= MCI_CMDR_RSPTYP_48;
}
/*
* If there is no data transfer, just set up the right interrupt mask
* and start the command.
*
* The interrupt mask needs to be CMDRDY plus all non-data-transfer
* errors. It's important to leave the transfer-related errors out, to
* avoid spurious timeout or crc errors on a STOP command following a
* multiblock read. When a multiblock read is in progress, sending a
* STOP in the middle of a block occasionally triggers such errors, but
* we're totally disinterested in them because we've already gotten all
* the data we wanted without error before sending the STOP command.
*/
if (data == NULL) {
uint32_t ier = MCI_SR_CMDRDY |
MCI_SR_RTOE | MCI_SR_RENDE |
MCI_SR_RCRCE | MCI_SR_RDIRE | MCI_SR_RINDE;
at91_mci_pdc_disable(sc);
if (cmd->opcode == MMC_STOP_TRANSMISSION)
cmdr |= MCI_CMDR_TRCMD_STOP;
/* Ignore response CRC on CMD2 and ACMD41, per standard. */
if (cmd->opcode == MMC_SEND_OP_COND ||
cmd->opcode == ACMD_SD_SEND_OP_COND)
ier &= ~MCI_SR_RCRCE;
if (mci_debug)
printf("CMDR %x (opcode %d) ARGR %x no data\n",
cmdr, cmd->opcode, cmd->arg);
WR4(sc, MCI_ARGR, cmd->arg);
WR4(sc, MCI_CMDR, cmdr);
WR4(sc, MCI_IDR, 0xffffffff);
WR4(sc, MCI_IER, ier);
return;
}
/* There is data, set up the transfer-related parts of the command. */
if (data->flags & MMC_DATA_READ)
cmdr |= MCI_CMDR_TRDIR;
if (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE))
cmdr |= MCI_CMDR_TRCMD_START;
if (data->flags & MMC_DATA_STREAM)
cmdr |= MCI_CMDR_TRTYP_STREAM;
else if (data->flags & MMC_DATA_MULTI) {
cmdr |= MCI_CMDR_TRTYP_MULTIPLE;
sc->flags |= (data->flags & MMC_DATA_READ) ?
CMD_MULTIREAD : CMD_MULTIWRITE;
}
/*
* Disable PDC until we're ready.
*
* Set block size and turn on PDC mode for dma xfer.
* Note that the block size is the smaller of the amount of data to be
* transferred, or 512 bytes. The 512 size is fixed by the standard;
* smaller blocks are possible, but never larger.
*/
WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
mr = RD4(sc,MCI_MR) & ~MCI_MR_BLKLEN;
mr |= min(data->len, 512) << 16;
WR4(sc, MCI_MR, mr | MCI_MR_PDCMODE|MCI_MR_PDCPADV);
/*
* Set up DMA.
*
* Use bounce buffers even if we don't need to byteswap, because doing
* multi-block IO with large DMA buffers is way fast (compared to
* single-block IO), even after incurring the overhead of also copying
* from/to the caller's buffers (which may be in non-contiguous physical
* pages).
*
* In an ideal non-byteswap world we could create a dma tag that allows
* for discontiguous segments and do the IO directly from/to the
* caller's buffer(s), using ENDRX/ENDTX interrupts to chain the
* discontiguous buffers through the PDC. Someday.
*
* If a read is bigger than 2k, split it in half so that we can start
* byte-swapping the first half while the second half is on the wire.
* It would be best if we could split it into 8k chunks, but we can't
* always keep up with the byte-swapping due to other system activity,
* and if an RXBUFF interrupt happens while we're still handling the
* byte-swap from the prior buffer (IE, we haven't returned from
* handling the prior interrupt yet), then data will get dropped on the
* floor and we can't easily recover from that. The right fix for that
* would be to have the interrupt handling only keep the DMA flowing and
* enqueue filled buffers to be byte-swapped in a non-interrupt context.
* Even that won't work on the write side of things though; in that
* context we have to have all the data ready to go before starting the
* dma.
*
* XXX what about stream transfers?
*/
sc->xfer_offset = 0;
sc->bbuf_curidx = 0;
if (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) {
uint32_t len;
uint32_t remaining = data->len;
bus_addr_t paddr;
int err;
if (remaining > (BBCOUNT*BBSIZE))
panic("IO read size exceeds MAXDATA\n");
if (data->flags & MMC_DATA_READ) {
if (remaining > 2048) // XXX
len = remaining / 2;
else
len = remaining;
err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[0],
sc->bbuf_vaddr[0], len, at91_mci_getaddr,
&paddr, BUS_DMA_NOWAIT);
if (err != 0)
panic("IO read dmamap_load failed\n");
bus_dmamap_sync(sc->dmatag, sc->bbuf_map[0],
BUS_DMASYNC_PREREAD);
WR4(sc, PDC_RPR, paddr);
WR4(sc, PDC_RCR, len / 4);
sc->bbuf_len[0] = len;
remaining -= len;
if (remaining == 0) {
sc->bbuf_len[1] = 0;
} else {
len = remaining;
err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[1],
sc->bbuf_vaddr[1], len, at91_mci_getaddr,
&paddr, BUS_DMA_NOWAIT);
if (err != 0)
panic("IO read dmamap_load failed\n");
bus_dmamap_sync(sc->dmatag, sc->bbuf_map[1],
BUS_DMASYNC_PREREAD);
WR4(sc, PDC_RNPR, paddr);
WR4(sc, PDC_RNCR, len / 4);
sc->bbuf_len[1] = len;
remaining -= len;
}
WR4(sc, PDC_PTCR, PDC_PTCR_RXTEN);
} else {
len = min(BBSIZE, remaining);
at91_bswap_buf(sc, sc->bbuf_vaddr[0], data->data, len);
err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[0],
sc->bbuf_vaddr[0], len, at91_mci_getaddr,
&paddr, BUS_DMA_NOWAIT);
if (err != 0)
panic("IO write dmamap_load failed\n");
bus_dmamap_sync(sc->dmatag, sc->bbuf_map[0],
BUS_DMASYNC_PREWRITE);
/*
* Erratum workaround: PDC transfer length on a write
* must not be smaller than 12 bytes (3 words); only
* blklen bytes (set above) are actually transferred.
*/
WR4(sc, PDC_TPR,paddr);
WR4(sc, PDC_TCR, (len < 12) ? 3 : len / 4);
sc->bbuf_len[0] = len;
remaining -= len;
if (remaining == 0) {
sc->bbuf_len[1] = 0;
} else {
len = remaining;
at91_bswap_buf(sc, sc->bbuf_vaddr[1],
((char *)data->data)+BBSIZE, len);
err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[1],
sc->bbuf_vaddr[1], len, at91_mci_getaddr,
&paddr, BUS_DMA_NOWAIT);
if (err != 0)
panic("IO write dmamap_load failed\n");
bus_dmamap_sync(sc->dmatag, sc->bbuf_map[1],
BUS_DMASYNC_PREWRITE);
WR4(sc, PDC_TNPR, paddr);
WR4(sc, PDC_TNCR, (len < 12) ? 3 : len / 4);
sc->bbuf_len[1] = len;
remaining -= len;
}
/* do not enable PDC xfer until CMDRDY asserted */
}
data->xfer_len = 0; /* XXX what's this? appears to be unused. */
}
if (mci_debug)
printf("CMDR %x (opcode %d) ARGR %x with data len %d\n",
cmdr, cmd->opcode, cmd->arg, cmd->data->len);
WR4(sc, MCI_ARGR, cmd->arg);
WR4(sc, MCI_CMDR, cmdr);
WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_CMDRDY);
}
static void
at91_mci_next_operation(struct at91_mci_softc *sc)
{
struct mmc_request *req;
req = sc->req;
if (req == NULL)
return;
if (sc->flags & PENDING_CMD) {
sc->flags &= ~PENDING_CMD;
at91_mci_start_cmd(sc, req->cmd);
return;
} else if (sc->flags & PENDING_STOP) {
sc->flags &= ~PENDING_STOP;
at91_mci_start_cmd(sc, req->stop);
return;
}
WR4(sc, MCI_IDR, 0xffffffff);
sc->req = NULL;
sc->curcmd = NULL;
//printf("req done\n");
req->done(req);
}
static int
at91_mci_request(device_t brdev, device_t reqdev, struct mmc_request *req)
{
struct at91_mci_softc *sc = device_get_softc(brdev);
AT91_MCI_LOCK(sc);
if (sc->req != NULL) {
AT91_MCI_UNLOCK(sc);
return (EBUSY);
}
//printf("new req\n");
sc->req = req;
sc->flags = PENDING_CMD;
if (sc->req->stop)
sc->flags |= PENDING_STOP;
at91_mci_next_operation(sc);
AT91_MCI_UNLOCK(sc);
return (0);
}
static int
at91_mci_get_ro(device_t brdev, device_t reqdev)
{
return (0);
}
static int
at91_mci_acquire_host(device_t brdev, device_t reqdev)
{
struct at91_mci_softc *sc = device_get_softc(brdev);
int err = 0;
AT91_MCI_LOCK(sc);
while (sc->bus_busy)
msleep(sc, &sc->sc_mtx, PZERO, "mciah", hz / 5);
sc->bus_busy++;
AT91_MCI_UNLOCK(sc);
return (err);
}
static int
at91_mci_release_host(device_t brdev, device_t reqdev)
{
struct at91_mci_softc *sc = device_get_softc(brdev);
AT91_MCI_LOCK(sc);
sc->bus_busy--;
wakeup(sc);
AT91_MCI_UNLOCK(sc);
return (0);
}
static void
at91_mci_read_done(struct at91_mci_softc *sc, uint32_t sr)
{
struct mmc_command *cmd = sc->curcmd;
char * dataptr = (char *)cmd->data->data;
uint32_t curidx = sc->bbuf_curidx;
uint32_t len = sc->bbuf_len[curidx];
/*
* We arrive here when a DMA transfer for a read is done, whether it's
* a single or multi-block read.
*
* We byte-swap the buffer that just completed, and if that is the
* last buffer that's part of this read then we move on to the next
* operation, otherwise we wait for another ENDRX for the next bufer.
*/
bus_dmamap_sync(sc->dmatag, sc->bbuf_map[curidx], BUS_DMASYNC_POSTREAD);
bus_dmamap_unload(sc->dmatag, sc->bbuf_map[curidx]);
at91_bswap_buf(sc, dataptr + sc->xfer_offset, sc->bbuf_vaddr[curidx], len);
if (mci_debug) {
printf("read done sr %x curidx %d len %d xfer_offset %d\n",
sr, curidx, len, sc->xfer_offset);
}
sc->xfer_offset += len;
sc->bbuf_curidx = !curidx; /* swap buffers */
/*
* If we've transferred all the data, move on to the next operation.
*
* If we're still transferring the last buffer, RNCR is already zero but
* we have to write a zero anyway to clear the ENDRX status so we don't
* re-interrupt until the last buffer is done.
*/
if (sc->xfer_offset == cmd->data->len) {
WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
cmd->error = MMC_ERR_NONE;
at91_mci_next_operation(sc);
} else {
WR4(sc, PDC_RNCR, 0);
WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_ENDRX);
}
}
static void
at91_mci_write_done(struct at91_mci_softc *sc, uint32_t sr)
{
struct mmc_command *cmd = sc->curcmd;
/*
* We arrive here when the entire DMA transfer for a write is done,
* whether it's a single or multi-block write. If it's multi-block we
* have to immediately move on to the next operation which is to send
* the stop command. If it's a single-block transfer we need to wait
* for NOTBUSY, but if that's already asserted we can avoid another
* interrupt and just move on to completing the request right away.
*/
WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
bus_dmamap_sync(sc->dmatag, sc->bbuf_map[sc->bbuf_curidx],
BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->dmatag, sc->bbuf_map[sc->bbuf_curidx]);
if ((cmd->data->flags & MMC_DATA_MULTI) || (sr & MCI_SR_NOTBUSY)) {
cmd->error = MMC_ERR_NONE;
at91_mci_next_operation(sc);
} else {
WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_NOTBUSY);
}
}
static void
at91_mci_notbusy(struct at91_mci_softc *sc)
{
struct mmc_command *cmd = sc->curcmd;
/*
* We arrive here by either completion of a single-block write, or
* completion of the stop command that ended a multi-block write (and,
* I suppose, after a card-select or erase, but I haven't tested
* those). Anyway, we're done and it's time to move on to the next
* command.
*/
cmd->error = MMC_ERR_NONE;
at91_mci_next_operation(sc);
}
static void
at91_mci_stop_done(struct at91_mci_softc *sc, uint32_t sr)
{
struct mmc_command *cmd = sc->curcmd;