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musb_otg.c
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musb_otg.c
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/* $FreeBSD$ */
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Thanks to Mentor Graphics for providing a reference driver for this USB chip
* at their homepage.
*/
/*
* This file contains the driver for the Mentor Graphics Inventra USB
* 2.0 High Speed Dual-Role controller.
*
*/
#ifdef USB_GLOBAL_INCLUDE_FILE
#include USB_GLOBAL_INCLUDE_FILE
#else
#include <sys/stdint.h>
#include <sys/stddef.h>
#include <sys/param.h>
#include <sys/queue.h>
#include <sys/types.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/bus.h>
#include <sys/module.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/condvar.h>
#include <sys/sysctl.h>
#include <sys/sx.h>
#include <sys/unistd.h>
#include <sys/callout.h>
#include <sys/malloc.h>
#include <sys/priv.h>
#include <dev/usb/usb.h>
#include <dev/usb/usbdi.h>
#define USB_DEBUG_VAR musbotgdebug
#include <dev/usb/usb_core.h>
#include <dev/usb/usb_debug.h>
#include <dev/usb/usb_busdma.h>
#include <dev/usb/usb_process.h>
#include <dev/usb/usb_transfer.h>
#include <dev/usb/usb_device.h>
#include <dev/usb/usb_hub.h>
#include <dev/usb/usb_util.h>
#include <dev/usb/usb_controller.h>
#include <dev/usb/usb_bus.h>
#endif /* USB_GLOBAL_INCLUDE_FILE */
#include <dev/usb/controller/musb_otg.h>
#define MUSBOTG_INTR_ENDPT 1
#define MUSBOTG_BUS2SC(bus) \
((struct musbotg_softc *)(((uint8_t *)(bus)) - \
USB_P2U(&(((struct musbotg_softc *)0)->sc_bus))))
#define MUSBOTG_PC2SC(pc) \
MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
#ifdef USB_DEBUG
static int musbotgdebug = 0;
static SYSCTL_NODE(_hw_usb, OID_AUTO, musbotg, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
"USB musbotg");
SYSCTL_INT(_hw_usb_musbotg, OID_AUTO, debug, CTLFLAG_RWTUN,
&musbotgdebug, 0, "Debug level");
#endif
#define MAX_NAK_TO 16
/* prototypes */
static const struct usb_bus_methods musbotg_bus_methods;
static const struct usb_pipe_methods musbotg_device_bulk_methods;
static const struct usb_pipe_methods musbotg_device_ctrl_methods;
static const struct usb_pipe_methods musbotg_device_intr_methods;
static const struct usb_pipe_methods musbotg_device_isoc_methods;
/* Control transfers: Device mode */
static musbotg_cmd_t musbotg_dev_ctrl_setup_rx;
static musbotg_cmd_t musbotg_dev_ctrl_data_rx;
static musbotg_cmd_t musbotg_dev_ctrl_data_tx;
static musbotg_cmd_t musbotg_dev_ctrl_status;
/* Control transfers: Host mode */
static musbotg_cmd_t musbotg_host_ctrl_setup_tx;
static musbotg_cmd_t musbotg_host_ctrl_data_rx;
static musbotg_cmd_t musbotg_host_ctrl_data_tx;
static musbotg_cmd_t musbotg_host_ctrl_status_rx;
static musbotg_cmd_t musbotg_host_ctrl_status_tx;
/* Bulk, Interrupt, Isochronous: Device mode */
static musbotg_cmd_t musbotg_dev_data_rx;
static musbotg_cmd_t musbotg_dev_data_tx;
/* Bulk, Interrupt, Isochronous: Host mode */
static musbotg_cmd_t musbotg_host_data_rx;
static musbotg_cmd_t musbotg_host_data_tx;
static void musbotg_device_done(struct usb_xfer *, usb_error_t);
static void musbotg_do_poll(struct usb_bus *);
static void musbotg_standard_done(struct usb_xfer *);
static void musbotg_interrupt_poll(struct musbotg_softc *);
static void musbotg_root_intr(struct musbotg_softc *);
static int musbotg_channel_alloc(struct musbotg_softc *, struct musbotg_td *td, uint8_t);
static void musbotg_channel_free(struct musbotg_softc *, struct musbotg_td *td);
static void musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on);
/*
* Here is a configuration that the chip supports.
*/
static const struct usb_hw_ep_profile musbotg_ep_profile[1] = {
[0] = {
.max_in_frame_size = 64,/* fixed */
.max_out_frame_size = 64, /* fixed */
.is_simplex = 1,
.support_control = 1,
}
};
static const struct musb_otg_ep_cfg musbotg_ep_default[] = {
{
.ep_end = 1,
.ep_fifosz_shift = 12,
.ep_fifosz_reg = MUSB2_VAL_FIFOSZ_4096 | MUSB2_MASK_FIFODB,
},
{
.ep_end = 7,
.ep_fifosz_shift = 10,
.ep_fifosz_reg = MUSB2_VAL_FIFOSZ_512 | MUSB2_MASK_FIFODB,
},
{
.ep_end = 15,
.ep_fifosz_shift = 7,
.ep_fifosz_reg = MUSB2_VAL_FIFOSZ_128,
},
{
.ep_end = -1,
},
};
static int
musbotg_channel_alloc(struct musbotg_softc *sc, struct musbotg_td *td, uint8_t is_tx)
{
int ch;
int ep;
ep = td->ep_no;
/* In device mode each EP got its own channel */
if (sc->sc_mode == MUSB2_DEVICE_MODE) {
musbotg_ep_int_set(sc, ep, 1);
return (ep);
}
/*
* All control transactions go through EP0
*/
if (ep == 0) {
if (sc->sc_channel_mask & (1 << 0))
return (-1);
sc->sc_channel_mask |= (1 << 0);
musbotg_ep_int_set(sc, ep, 1);
return (0);
}
for (ch = sc->sc_ep_max; ch != 0; ch--) {
if (sc->sc_channel_mask & (1 << ch))
continue;
/* check FIFO size requirement */
if (is_tx) {
if (td->max_frame_size >
sc->sc_hw_ep_profile[ch].max_in_frame_size)
continue;
} else {
if (td->max_frame_size >
sc->sc_hw_ep_profile[ch].max_out_frame_size)
continue;
}
sc->sc_channel_mask |= (1 << ch);
musbotg_ep_int_set(sc, ch, 1);
return (ch);
}
DPRINTFN(-1, "No available channels. Mask: %04x\n", sc->sc_channel_mask);
return (-1);
}
static void
musbotg_channel_free(struct musbotg_softc *sc, struct musbotg_td *td)
{
DPRINTFN(1, "ep_no=%d\n", td->channel);
if (sc->sc_mode == MUSB2_DEVICE_MODE)
return;
if (td == NULL)
return;
if (td->channel == -1)
return;
musbotg_ep_int_set(sc, td->channel, 0);
sc->sc_channel_mask &= ~(1 << td->channel);
td->channel = -1;
}
static void
musbotg_get_hw_ep_profile(struct usb_device *udev,
const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
{
struct musbotg_softc *sc;
sc = MUSBOTG_BUS2SC(udev->bus);
if (ep_addr == 0) {
/* control endpoint */
*ppf = musbotg_ep_profile;
} else if (ep_addr <= sc->sc_ep_max) {
/* other endpoints */
*ppf = sc->sc_hw_ep_profile + ep_addr;
} else {
*ppf = NULL;
}
}
static void
musbotg_clocks_on(struct musbotg_softc *sc)
{
if (sc->sc_flags.clocks_off &&
sc->sc_flags.port_powered) {
DPRINTFN(4, "\n");
if (sc->sc_clocks_on) {
(sc->sc_clocks_on) (sc->sc_clocks_arg);
}
sc->sc_flags.clocks_off = 0;
/* XXX enable Transceiver */
}
}
static void
musbotg_clocks_off(struct musbotg_softc *sc)
{
if (!sc->sc_flags.clocks_off) {
DPRINTFN(4, "\n");
/* XXX disable Transceiver */
if (sc->sc_clocks_off) {
(sc->sc_clocks_off) (sc->sc_clocks_arg);
}
sc->sc_flags.clocks_off = 1;
}
}
static void
musbotg_pull_common(struct musbotg_softc *sc, uint8_t on)
{
uint8_t temp;
temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
if (on)
temp |= MUSB2_MASK_SOFTC;
else
temp &= ~MUSB2_MASK_SOFTC;
MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
}
static void
musbotg_pull_up(struct musbotg_softc *sc)
{
/* pullup D+, if possible */
if (!sc->sc_flags.d_pulled_up &&
sc->sc_flags.port_powered) {
sc->sc_flags.d_pulled_up = 1;
musbotg_pull_common(sc, 1);
}
}
static void
musbotg_pull_down(struct musbotg_softc *sc)
{
/* pulldown D+, if possible */
if (sc->sc_flags.d_pulled_up) {
sc->sc_flags.d_pulled_up = 0;
musbotg_pull_common(sc, 0);
}
}
static void
musbotg_suspend_host(struct musbotg_softc *sc)
{
uint8_t temp;
if (sc->sc_flags.status_suspend) {
return;
}
temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
temp |= MUSB2_MASK_SUSPMODE;
MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
sc->sc_flags.status_suspend = 1;
}
static void
musbotg_wakeup_host(struct musbotg_softc *sc)
{
uint8_t temp;
if (!(sc->sc_flags.status_suspend)) {
return;
}
temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
temp &= ~MUSB2_MASK_SUSPMODE;
temp |= MUSB2_MASK_RESUME;
MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
/* wait 20 milliseconds */
/* Wait for reset to complete. */
usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
temp &= ~MUSB2_MASK_RESUME;
MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
sc->sc_flags.status_suspend = 0;
}
static void
musbotg_wakeup_peer(struct musbotg_softc *sc)
{
uint8_t temp;
if (!(sc->sc_flags.status_suspend)) {
return;
}
temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
temp |= MUSB2_MASK_RESUME;
MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
/* wait 8 milliseconds */
/* Wait for reset to complete. */
usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
temp &= ~MUSB2_MASK_RESUME;
MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
}
static void
musbotg_set_address(struct musbotg_softc *sc, uint8_t addr)
{
DPRINTFN(4, "addr=%d\n", addr);
addr &= 0x7F;
MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr);
}
static uint8_t
musbotg_dev_ctrl_setup_rx(struct musbotg_td *td)
{
struct musbotg_softc *sc;
struct usb_device_request req;
uint16_t count;
uint8_t csr;
/* get pointer to softc */
sc = MUSBOTG_PC2SC(td->pc);
if (td->channel == -1)
td->channel = musbotg_channel_alloc(sc, td, 0);
/* EP0 is busy, wait */
if (td->channel == -1)
return (1);
DPRINTFN(1, "ep_no=%d\n", td->channel);
/* select endpoint 0 */
MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
/* read out FIFO status */
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
DPRINTFN(4, "csr=0x%02x\n", csr);
/*
* NOTE: If DATAEND is set we should not call the
* callback, hence the status stage is not complete.
*/
if (csr & MUSB2_MASK_CSR0L_DATAEND) {
/* do not stall at this point */
td->did_stall = 1;
/* wait for interrupt */
DPRINTFN(1, "CSR0 DATAEND\n");
goto not_complete;
}
if (csr & MUSB2_MASK_CSR0L_SENTSTALL) {
/* clear SENTSTALL */
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
/* get latest status */
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
/* update EP0 state */
sc->sc_ep0_busy = 0;
}
if (csr & MUSB2_MASK_CSR0L_SETUPEND) {
/* clear SETUPEND */
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
MUSB2_MASK_CSR0L_SETUPEND_CLR);
/* get latest status */
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
/* update EP0 state */
sc->sc_ep0_busy = 0;
}
if (sc->sc_ep0_busy) {
DPRINTFN(1, "EP0 BUSY\n");
goto not_complete;
}
if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
goto not_complete;
}
/* get the packet byte count */
count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
/* verify data length */
if (count != td->remainder) {
DPRINTFN(1, "Invalid SETUP packet "
"length, %d bytes\n", count);
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
/* don't clear stall */
td->did_stall = 1;
goto not_complete;
}
if (count != sizeof(req)) {
DPRINTFN(1, "Unsupported SETUP packet "
"length, %d bytes\n", count);
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
/* don't clear stall */
td->did_stall = 1;
goto not_complete;
}
/* clear did stall flag */
td->did_stall = 0;
/* receive data */
bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req));
/* copy data into real buffer */
usbd_copy_in(td->pc, 0, &req, sizeof(req));
td->offset = sizeof(req);
td->remainder = 0;
/* set pending command */
sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
/* we need set stall or dataend after this */
sc->sc_ep0_busy = 1;
/* sneak peek the set address */
if ((req.bmRequestType == UT_WRITE_DEVICE) &&
(req.bRequest == UR_SET_ADDRESS)) {
sc->sc_dv_addr = req.wValue[0] & 0x7F;
} else {
sc->sc_dv_addr = 0xFF;
}
musbotg_channel_free(sc, td);
return (0); /* complete */
not_complete:
/* abort any ongoing transfer */
if (!td->did_stall) {
DPRINTFN(4, "stalling\n");
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
MUSB2_MASK_CSR0L_SENDSTALL);
td->did_stall = 1;
}
return (1); /* not complete */
}
static uint8_t
musbotg_host_ctrl_setup_tx(struct musbotg_td *td)
{
struct musbotg_softc *sc;
struct usb_device_request req;
uint8_t csr, csrh;
/* get pointer to softc */
sc = MUSBOTG_PC2SC(td->pc);
if (td->channel == -1)
td->channel = musbotg_channel_alloc(sc, td, 1);
/* EP0 is busy, wait */
if (td->channel == -1)
return (1);
DPRINTFN(1, "ep_no=%d\n", td->channel);
/* select endpoint 0 */
MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
/* read out FIFO status */
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
DPRINTFN(4, "csr=0x%02x\n", csr);
/* Not ready yet yet */
if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
return (1);
/* Failed */
if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
MUSB2_MASK_CSR0L_ERROR))
{
/* Clear status bit */
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
td->error = 1;
}
if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
DPRINTFN(1, "NAK timeout\n");
if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
csrh |= MUSB2_MASK_CSR0H_FFLUSH;
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
csrh |= MUSB2_MASK_CSR0H_FFLUSH;
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
}
}
csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
td->error = 1;
}
if (td->error) {
musbotg_channel_free(sc, td);
return (0);
}
/* Fifo is not empty and there is no NAK timeout */
if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
return (1);
/* check if we are complete */
if (td->remainder == 0) {
/* we are complete */
musbotg_channel_free(sc, td);
return (0);
}
/* copy data into real buffer */
usbd_copy_out(td->pc, 0, &req, sizeof(req));
/* send data */
bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req));
/* update offset and remainder */
td->offset += sizeof(req);
td->remainder -= sizeof(req);
MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
/* write command */
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
MUSB2_MASK_CSR0L_TXPKTRDY |
MUSB2_MASK_CSR0L_SETUPPKT);
/* Just to be consistent, not used above */
td->transaction_started = 1;
return (1); /* in progress */
}
/* Control endpoint only data handling functions (RX/TX/SYNC) */
static uint8_t
musbotg_dev_ctrl_data_rx(struct musbotg_td *td)
{
struct usb_page_search buf_res;
struct musbotg_softc *sc;
uint16_t count;
uint8_t csr;
uint8_t got_short;
/* get pointer to softc */
sc = MUSBOTG_PC2SC(td->pc);
/* select endpoint 0 */
MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
/* check if a command is pending */
if (sc->sc_ep0_cmd) {
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
sc->sc_ep0_cmd = 0;
}
/* read out FIFO status */
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
DPRINTFN(4, "csr=0x%02x\n", csr);
got_short = 0;
if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
MUSB2_MASK_CSR0L_SENTSTALL)) {
if (td->remainder == 0) {
/*
* We are actually complete and have
* received the next SETUP
*/
DPRINTFN(4, "faking complete\n");
return (0); /* complete */
}
/*
* USB Host Aborted the transfer.
*/
td->error = 1;
return (0); /* complete */
}
if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
return (1); /* not complete */
}
/* get the packet byte count */
count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
/* verify the packet byte count */
if (count != td->max_frame_size) {
if (count < td->max_frame_size) {
/* we have a short packet */
td->short_pkt = 1;
got_short = 1;
} else {
/* invalid USB packet */
td->error = 1;
return (0); /* we are complete */
}
}
/* verify the packet byte count */
if (count > td->remainder) {
/* invalid USB packet */
td->error = 1;
return (0); /* we are complete */
}
while (count > 0) {
uint32_t temp;
usbd_get_page(td->pc, td->offset, &buf_res);
/* get correct length */
if (buf_res.length > count) {
buf_res.length = count;
}
/* check for unaligned memory address */
if (USB_P2U(buf_res.buffer) & 3) {
temp = count & ~3;
if (temp) {
/* receive data 4 bytes at a time */
bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
temp / 4);
}
temp = count & 3;
if (temp) {
/* receive data 1 byte at a time */
bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
MUSB2_REG_EPFIFO(0),
(void *)(&sc->sc_bounce_buf[count / 4]), temp);
}
usbd_copy_in(td->pc, td->offset,
sc->sc_bounce_buf, count);
/* update offset and remainder */
td->offset += count;
td->remainder -= count;
break;
}
/* check if we can optimise */
if (buf_res.length >= 4) {
/* receive data 4 bytes at a time */
bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
MUSB2_REG_EPFIFO(0), buf_res.buffer,
buf_res.length / 4);
temp = buf_res.length & ~3;
/* update counters */
count -= temp;
td->offset += temp;
td->remainder -= temp;
continue;
}
/* receive data */
bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
/* update counters */
count -= buf_res.length;
td->offset += buf_res.length;
td->remainder -= buf_res.length;
}
/* check if we are complete */
if ((td->remainder == 0) || got_short) {
if (td->short_pkt) {
/* we are complete */
sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
return (0);
}
/* else need to receive a zero length packet */
}
/* write command - need more data */
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
return (1); /* not complete */
}
static uint8_t
musbotg_dev_ctrl_data_tx(struct musbotg_td *td)
{
struct usb_page_search buf_res;
struct musbotg_softc *sc;
uint16_t count;
uint8_t csr;
/* get pointer to softc */
sc = MUSBOTG_PC2SC(td->pc);
/* select endpoint 0 */
MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
/* check if a command is pending */
if (sc->sc_ep0_cmd) {
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
sc->sc_ep0_cmd = 0;
}
/* read out FIFO status */
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
DPRINTFN(4, "csr=0x%02x\n", csr);
if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
MUSB2_MASK_CSR0L_SENTSTALL)) {
/*
* The current transfer was aborted
* by the USB Host
*/
td->error = 1;
return (0); /* complete */
}
if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) {
return (1); /* not complete */
}
count = td->max_frame_size;
if (td->remainder < count) {
/* we have a short packet */
td->short_pkt = 1;
count = td->remainder;
}
while (count > 0) {
uint32_t temp;
usbd_get_page(td->pc, td->offset, &buf_res);
/* get correct length */
if (buf_res.length > count) {
buf_res.length = count;
}
/* check for unaligned memory address */
if (USB_P2U(buf_res.buffer) & 3) {
usbd_copy_out(td->pc, td->offset,
sc->sc_bounce_buf, count);
temp = count & ~3;
if (temp) {
/* transmit data 4 bytes at a time */
bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
temp / 4);
}
temp = count & 3;
if (temp) {
/* receive data 1 byte at a time */
bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
MUSB2_REG_EPFIFO(0),
((void *)&sc->sc_bounce_buf[count / 4]), temp);
}
/* update offset and remainder */
td->offset += count;
td->remainder -= count;
break;
}
/* check if we can optimise */
if (buf_res.length >= 4) {
/* transmit data 4 bytes at a time */
bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
MUSB2_REG_EPFIFO(0), buf_res.buffer,
buf_res.length / 4);
temp = buf_res.length & ~3;
/* update counters */
count -= temp;
td->offset += temp;
td->remainder -= temp;
continue;
}
/* transmit data */
bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
/* update counters */
count -= buf_res.length;
td->offset += buf_res.length;
td->remainder -= buf_res.length;
}
/* check remainder */
if (td->remainder == 0) {
if (td->short_pkt) {
sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY;
return (0); /* complete */
}
/* else we need to transmit a short packet */
}
/* write command */
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
MUSB2_MASK_CSR0L_TXPKTRDY);
return (1); /* not complete */
}
static uint8_t
musbotg_host_ctrl_data_rx(struct musbotg_td *td)
{
struct usb_page_search buf_res;
struct musbotg_softc *sc;
uint16_t count;
uint8_t csr;
uint8_t got_short;
/* get pointer to softc */
sc = MUSBOTG_PC2SC(td->pc);
if (td->channel == -1)
td->channel = musbotg_channel_alloc(sc, td, 0);
/* EP0 is busy, wait */
if (td->channel == -1)
return (1);
DPRINTFN(1, "ep_no=%d\n", td->channel);
/* select endpoint 0 */
MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
/* read out FIFO status */
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
DPRINTFN(4, "csr=0x%02x\n", csr);
got_short = 0;
if (!td->transaction_started) {
td->transaction_started = 1;
MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0),
td->dev_addr);
MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr);
MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport);
MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
MUSB2_MASK_CSR0L_REQPKT);
return (1);
}
if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
csr &= ~MUSB2_MASK_CSR0L_REQPKT;
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
td->error = 1;
}
/* Failed */
if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
MUSB2_MASK_CSR0L_ERROR))
{
/* Clear status bit */
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
td->error = 1;
}
if (td->error) {
musbotg_channel_free(sc, td);
return (0); /* we are complete */
}
if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY))
return (1); /* not yet */
/* get the packet byte count */
count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
/* verify the packet byte count */
if (count != td->max_frame_size) {
if (count < td->max_frame_size) {
/* we have a short packet */
td->short_pkt = 1;
got_short = 1;
} else {
/* invalid USB packet */
td->error = 1;
musbotg_channel_free(sc, td);
return (0); /* we are complete */
}
}
/* verify the packet byte count */
if (count > td->remainder) {
/* invalid USB packet */
td->error = 1;
musbotg_channel_free(sc, td);
return (0); /* we are complete */
}
while (count > 0) {
uint32_t temp;
usbd_get_page(td->pc, td->offset, &buf_res);
/* get correct length */
if (buf_res.length > count) {
buf_res.length = count;
}
/* check for unaligned memory address */
if (USB_P2U(buf_res.buffer) & 3) {
temp = count & ~3;