weird compile result.

[RyanSangdeokPark]

it's weird compile result is occurred In the '2.2_comb_logic' chapter

In the case of addition of this example, io.out_add should be 4'h8(or 4'b1000), but it's 4'h0 in the generated verilog code.
I want to make sure whether I missed something or not.
or, is this a kind of bug?
for your reference, I ran this one on Jupyter notebook

[edwardcwang]

If you try with something like the following, what is the resultant Verilog?

val temp = WireDefault(4.U + 4.U)
io.out_add := temp

This happens because of FIRRTL-level optimization.

[RyanSangdeokPark]

If you try with something like the following, what is the resultant Verilog?

val temp = WireDefault(4.U + 4.U)
io.out_add := temp

This happens because of FIRRTL-level optimization.

Hi edwardcwang,

I've got same result.

Thanks

[edwardcwang]

@Ryan-Sangdeok-Park Thanks for the catch, and thank you for your interest in Chisel! Looks like I was mistaken - try 4.U +& 4.U instead. It turns out that 4.U + 4.U is equivalent to 4.U(3.W) + 4.U(3.W) which does result in a truncated result (the + operator truncates by default) of 0. Please take a look at chipsalliance/chisel#1144 if you are interested in what's going on behind the scenes.

[RyanSangdeokPark]

@Ryan-Sangdeok-Park Thanks for the catch, and thank you for your interest in Chisel! Looks like I was mistaken - try 4.U +& 4.U instead. It turns out that 4.U + 4.U is equivalent to 4.U(3.W) + 4.U(3.W) which does result in a truncated result (the + operator truncates by default) of 0. Please take a look at freechipsproject/chisel3#1144 if you are interested in what's going on behind the scenes.

I've check and compile result is what expected!
This is so interesting, and powerful language I think.
It seems so strict and many operators, but I believe it makes less error situation.

Thanks.