build.v

/* Automatically generated by Amaranth 0.4.dev33+gdb24a14. Do not edit. */
/* Generated by Amaranth Yosys 0.10.0 (PyPI ver 0.10.0.dev47, git sha1 dca8fb54a) */

module litex_soc(soc_clk, sdram_clk, uart_0__rx__i, uart_0__tx__o, sdram_0__clk__io, sdram_0__clk_en__io, sdram_0__cs__io, sdram_0__we__io, sdram_0__ras__io, sdram_0__cas__io, sdram_0__ba__io, sdram_0__a__io, sdram_0__dqm__io, sdram_0__dq__io, led);
  output led;
  output [12:0] sdram_0__a__io;
  output [1:0] sdram_0__ba__io;
  output sdram_0__cas__io;
  output sdram_0__clk__io;
  output sdram_0__clk_en__io;
  output sdram_0__cs__io;
  inout [15:0] sdram_0__dq__io;
  output [1:0] sdram_0__dqm__io;
  output sdram_0__ras__io;
  output sdram_0__we__io;
  input sdram_clk;
  input soc_clk;
  input uart_0__rx__i;
  output uart_0__tx__o;
  qmtech_5cefa2 litex_soc (
    .clk105(soc_clk),
    .clk105_ram(sdram_clk),
    .sdram_a(sdram_0__a__io),
    .sdram_ba(sdram_0__ba__io),
    .sdram_cas_n(sdram_0__cas__io),
    .sdram_cke(sdram_0__clk_en__io),
    .sdram_clock(sdram_0__clk__io),
    .sdram_cs_n(sdram_0__cs__io),
    .sdram_dm(sdram_0__dqm__io),
    .sdram_dq(sdram_0__dq__io),
    .sdram_ras_n(sdram_0__ras__io),
    .sdram_we_n(sdram_0__we__io),
    .serial_rx(uart_0__rx__i),
    .serial_tx(uart_0__tx__o),
    .user_led0(led)
  );
endmodule

module pin_button_0(button_0__io, button_0__i);
  wire \$1 ;
  output button_0__i;
  wire button_0__i_neg;
  input button_0__io;
  assign \$1  = ~ button_0__i_neg;
  altiobuf_in #(
    .enable_bus_hold("FALSE"),
    .number_of_channels(32'd1),
    .use_differential_mode("FALSE")
  ) button_0 (
    .datain(button_0__io),
    .dataout(button_0__i_neg)
  );
  assign button_0__i = \$1 ;
endmodule

module pin_button_1(button_1__io, button_1__i);
  wire \$1 ;
  output button_1__i;
  wire button_1__i_neg;
  input button_1__io;
  assign \$1  = ~ button_1__i_neg;
  altiobuf_in #(
    .enable_bus_hold("FALSE"),
    .number_of_channels(32'd1),
    .use_differential_mode("FALSE")
  ) button_1 (
    .datain(button_1__io),
    .dataout(button_1__i_neg)
  );
  assign button_1__i = \$1 ;
endmodule

module pin_clk50_0(clk50_0__io, clk50_0__i);
  (* keep = "true" *)
  output clk50_0__i;
  input clk50_0__io;
  altiobuf_in #(
    .enable_bus_hold("FALSE"),
    .number_of_channels(32'd1),
    .use_differential_mode("FALSE")
  ) clk50_0 (
    .datain(clk50_0__io),
    .dataout(clk50_0__i)
  );
endmodule

module pin_led_0(led_0__io, led_0__o);
  output led_0__io;
  input led_0__o;
  altiobuf_out #(
    .enable_bus_hold("FALSE"),
    .number_of_channels(32'd1),
    .use_differential_mode("FALSE"),
    .use_oe("FALSE")
  ) led_0 (
    .datain(led_0__o),
    .dataout(led_0__io)
  );
endmodule

module pin_led_1(led_1__io, led_1__o);
  output led_1__io;
  input led_1__o;
  altiobuf_out #(
    .enable_bus_hold("FALSE"),
    .number_of_channels(32'd1),
    .use_differential_mode("FALSE"),
    .use_oe("FALSE")
  ) led_1 (
    .datain(led_1__o),
    .dataout(led_1__io)
  );
endmodule

module pin_uart_0__rx(uart_0__rx__io, uart_0__rx__i);
  output uart_0__rx__i;
  input uart_0__rx__io;
  altiobuf_in #(
    .enable_bus_hold("FALSE"),
    .number_of_channels(32'd1),
    .use_differential_mode("FALSE")
  ) uart_0__rx (
    .datain(uart_0__rx__io),
    .dataout(uart_0__rx__i)
  );
endmodule

module pin_uart_0__tx(uart_0__tx__io, uart_0__tx__o);
  output uart_0__tx__io;
  input uart_0__tx__o;
  altiobuf_out #(
    .enable_bus_hold("FALSE"),
    .number_of_channels(32'd1),
    .use_differential_mode("FALSE"),
    .use_oe("FALSE")
  ) uart_0__tx (
    .datain(uart_0__tx__o),
    .dataout(uart_0__tx__io)
  );
endmodule

module pll(clk, soc_clk, sdram_clk, clk50_0__i, rst);
  wire \$1 ;
  wire \$2 ;
  output clk;
  (* keep = "true" *)
  input clk50_0__i;
  wire main_clock;
  wire reset_sync_sync_reset;
  output rst;
  output sdram_clk;
  wire [1:0] sdram_clocks;
  wire sdram_locked;
  output soc_clk;
  wire sys_locked;
  assign \$2  = sys_locked & sdram_locked;
  assign \$1  = ~ \$2 ;
  altera_pll #(
    .fractional_vco_multiplier("true"),
    .number_of_clocks("2"),
    .operation_mode("normal"),
    .output_clock_frequency0("109.226666 MHz"),
    .output_clock_frequency1("109.226666 MHz"),
    .phase_shift1("253 ps"),
    .pll_subtype("General"),
    .pll_type("General"),
    .reference_clock_frequency("60.0 MHz")
  ) audiopll (
    .locked(sdram_locked),
    .outclk(sdram_clocks),
    .refclk(main_clock)
  );
  altera_pll #(
    .fractional_vco_multiplier("false"),
    .number_of_clocks("1"),
    .operation_mode("normal"),
    .output_clock_frequency0("60.000000 MHz"),
    .pll_subtype("General"),
    .pll_type("General"),
    .reference_clock_frequency("50.0 MHz")
  ) mainpll (
    .locked(sys_locked),
    .outclk(main_clock),
    .refclk(clk50_0__i)
  );
  reset_sync_sdram reset_sync_sdram (
    .reset(reset_sync_sync_reset),
    .sdram_clk(sdram_clk)
  );
  reset_sync_soc reset_sync_soc (
    .reset(reset_sync_sync_reset),
    .soc_clk(soc_clk)
  );
  reset_sync_sync reset_sync_sync (
    .clk(clk),
    .reset(reset_sync_sync_reset),
    .rst(rst)
  );
  assign sdram_clk = sdram_clocks[1];
  assign soc_clk = sdram_clocks[0];
  assign clk = main_clock;
  assign reset_sync_sync_reset = \$1 ;
endmodule

module reset_sync_sdram(sdram_clk, reset);
  wire \$1 ;
  wire \$3 ;
  input reset;
  input sdram_clk;
  wire sdram_rst;
  wire sync_output;
  assign \$1  = ~ reset;
  assign \$3  = ~ sync_output;
  altera_std_synchronizer #(
    .depth(32'd2)
  ) \U$$0  (
    .clk(sdram_clk),
    .din(1'h1),
    .dout(sync_output),
    .reset_n(\$1 )
  );
  assign sdram_rst = \$3 ;
endmodule

module reset_sync_soc(soc_clk, reset);
  wire \$1 ;
  wire \$3 ;
  input reset;
  input soc_clk;
  wire soc_rst;
  wire sync_output;
  assign \$1  = ~ reset;
  assign \$3  = ~ sync_output;
  altera_std_synchronizer #(
    .depth(32'd2)
  ) \U$$0  (
    .clk(soc_clk),
    .din(1'h1),
    .dout(sync_output),
    .reset_n(\$1 )
  );
  assign soc_rst = \$3 ;
endmodule

module reset_sync_sync(clk, reset, rst);
  wire \$1 ;
  wire \$3 ;
  input clk;
  input reset;
  output rst;
  wire sync_output;
  assign \$1  = ~ reset;
  assign \$3  = ~ sync_output;
  altera_std_synchronizer #(
    .depth(32'd2)
  ) \U$$0  (
    .clk(clk),
    .din(1'h1),
    .dout(sync_output),
    .reset_n(\$1 )
  );
  assign rst = \$3 ;
endmodule

module top(led_0__io, led_1__io, button_0__io, button_1__io, clk50_0__io, sdram_0__clk__io, sdram_0__clk_en__io, sdram_0__cs__io, sdram_0__we__io, sdram_0__ras__io, sdram_0__cas__io, sdram_0__ba__io, sdram_0__a__io, sdram_0__dqm__io, uart_0__rx__io, uart_0__tx__io, sdram_0__dq__io);
  reg \initial  = 0;
  wire [1:0] \$1 ;
  wire [25:0] \$10 ;
  wire [25:0] \$11 ;
  wire \$13 ;
  wire [1:0] \$15 ;
  wire \$2 ;
  wire \$4 ;
  wire [1:0] \$6 ;
  wire \$8 ;
  input button_0__io;
  input button_1__io;
  wire clk;
  input clk50_0__io;
  reg [1:0] flops = 2'h0;
  reg [1:0] \flops$next ;
  output led_0__io;
  output led_1__io;
  wire litex_soc_led;
  wire litex_soc_uart_0__rx__i;
  wire litex_soc_uart_0__tx__o;
  wire pin_button_0_button_0__i;
  wire pin_button_1_button_1__i;
  wire pin_led_0_led_0__o;
  wire pin_led_1_led_1__o;
  (* keep = "true" *)
  wire pll_clk50_0__i;
  wire pll_sdram_clk;
  wire pll_soc_clk;
  wire rst;
  output [12:0] sdram_0__a__io;
  output [1:0] sdram_0__ba__io;
  output sdram_0__cas__io;
  output sdram_0__clk__io;
  output sdram_0__clk_en__io;
  output sdram_0__cs__io;
  inout [15:0] sdram_0__dq__io;
  output [1:0] sdram_0__dqm__io;
  output sdram_0__ras__io;
  output sdram_0__we__io;
  reg [24:0] timer = 25'h17d783f;
  reg [24:0] \timer$next ;
  input uart_0__rx__io;
  output uart_0__tx__io;
  assign \$11  = timer - 1'h1;
  assign \$13  = ! timer;
  assign \$15  = ~ flops;
  always @(posedge clk)
    timer <= \timer$next ;
  always @(posedge clk)
    flops <= \flops$next ;
  assign \$6  = flops ^ { \$4 , \$2  };
  assign \$8  = ! timer;
  litex_soc litex_soc (
    .led(litex_soc_led),
    .sdram_0__a__io(sdram_0__a__io),
    .sdram_0__ba__io(sdram_0__ba__io),
    .sdram_0__cas__io(sdram_0__cas__io),
    .sdram_0__clk__io(sdram_0__clk__io),
    .sdram_0__clk_en__io(sdram_0__clk_en__io),
    .sdram_0__cs__io(sdram_0__cs__io),
    .sdram_0__dq__io(sdram_0__dq__io),
    .sdram_0__dqm__io(sdram_0__dqm__io),
    .sdram_0__ras__io(sdram_0__ras__io),
    .sdram_0__we__io(sdram_0__we__io),
    .sdram_clk(pll_sdram_clk),
    .soc_clk(pll_soc_clk),
    .uart_0__rx__i(litex_soc_uart_0__rx__i),
    .uart_0__tx__o(litex_soc_uart_0__tx__o)
  );
  pin_button_0 pin_button_0 (
    .button_0__i(pin_button_0_button_0__i),
    .button_0__io(button_0__io)
  );
  pin_button_1 pin_button_1 (
    .button_1__i(pin_button_1_button_1__i),
    .button_1__io(button_1__io)
  );
  pin_clk50_0 pin_clk50_0 (
    .clk50_0__i(pll_clk50_0__i),
    .clk50_0__io(clk50_0__io)
  );
  pin_led_0 pin_led_0 (
    .led_0__io(led_0__io),
    .led_0__o(pin_led_0_led_0__o)
  );
  pin_led_1 pin_led_1 (
    .led_1__io(led_1__io),
    .led_1__o(pin_led_1_led_1__o)
  );
  pin_uart_0__rx pin_uart_0__rx (
    .uart_0__rx__i(litex_soc_uart_0__rx__i),
    .uart_0__rx__io(uart_0__rx__io)
  );
  pin_uart_0__tx pin_uart_0__tx (
    .uart_0__tx__io(uart_0__tx__io),
    .uart_0__tx__o(litex_soc_uart_0__tx__o)
  );
  pll pll (
    .clk(clk),
    .clk50_0__i(pll_clk50_0__i),
    .rst(rst),
    .sdram_clk(pll_sdram_clk),
    .soc_clk(pll_soc_clk)
  );
  always @* begin
    if (\initial ) begin end
    (* full_case = 32'd1 *)
    casez (\$8 )
      1'h1:
          \timer$next  = 25'h17d783f;
      default:
          \timer$next  = \$11 [24:0];
    endcase
    casez (rst)
      1'h1:
          \timer$next  = 25'h17d783f;
    endcase
  end
  always @* begin
    if (\initial ) begin end
    \flops$next  = flops;
    casez (\$13 )
      1'h1:
          \flops$next  = \$15 ;
    endcase
    casez (rst)
      1'h1:
          \flops$next  = 2'h0;
    endcase
  end
  assign \$1  = \$6 ;
  assign \$10  = \$11 ;
  assign pin_led_0_led_0__o = litex_soc_led;
  assign pin_led_1_led_1__o = \$6 [0];
  assign \$2  = pin_button_0_button_0__i;
  assign \$4  = pin_button_1_button_1__i;
endmodule